ASIC and FPGA Verification - A Guide to Component Modeling (Paperback)

Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today s digital designs.
ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.
*Provides numerous models and a clearly defined methodology for performing board-level simulation.
*Covers the details of modeling for verification of both logic and timing.
*First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.

General

Imprint:	Morgan Kaufmann Publishers In
Country of origin:	United States
Series:	Systems on Silicon
Release date:	September 2004
First published:	October 2004
Authors:	Richard Munden
Dimensions:	235 x 191 x 24mm (L x W x T)
Format:	Paperback
Pages:	336
ISBN-13:	978-0-12-510581-1
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Electronic devices & materials > General Books > Academic & Education > Professional & Technical > Computing Promotions
LSN:	0-12-510581-9
Barcode:	9780125105811

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