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Low Power Interconnect Design (Hardcover, 2012) Loot Price: R2,866
Discovery Miles 28 660
Repayment Terms: R269 pm x 12*
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Low Power Interconnect Design (Hardcover, 2012): Sandeep Saini

Low Power Interconnect Design (Hardcover, 2012)

Sandeep Saini

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Loot Price R2,866 Discovery Miles 28 660 | Repayment Terms: R269 pm x 12*

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This book provides practical solutions for delay and power reduction for on-chip interconnects and buses. It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system. Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Release date: June 2015
First published: 2015
Authors: Sandeep Saini
Dimensions: 235 x 155 x 14mm (L x W x T)
Format: Hardcover
Pages: 152
Edition: 2012
ISBN-13: 978-1-4614-1322-6
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General
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LSN: 1-4614-1322-2
Barcode: 9781461413226

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