Hardware correctness is becoming ever more important in the design
of computer systems. The authors introduce a powerful new approach
to the design and analysis of modern computer architectures, based
on mathematically well-founded formal methods which allows for
rigorous correctness proofs, accurate hardware costs determination,
and performance evaluation. This book develops, at the gate level,
the complete design of a pipelined RISC processor with a fully
IEEE-compliant floating-point unit. In contrast to other design
approaches, the design presented here is modular, clean and
complete.
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