Time-interleaved Analog-to-Digital Converters describes the
research performed on low-power time-interleaved ADCs. A detailed
theoretical analysis is made of the time-interleaved Track &
Hold, since it must be capable of handling signals in the GHz range
with little distortion, and minimal power consumption. Timing
calibration is not attractive, therefore design techniques are
presented which do not require timing calibration. The design of
power efficient sub-ADCs is addressed with a theoretical analysis
of a successive approximation converter and a pipeline converter.
It turns out that the first can consume about 10 times less power
than the latter, and this conclusion is supported by literature.
Time-interleaved Analog-to-Digital Converters describes the design
of a high performance time-interleaved ADC, with much attention for
practical design aspects, aiming at both industry and research.
Measurements show best-inclass performance with a sample-rate of
1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step.
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