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RTL Modeling with SystemVerilog for Simulation and Synthesis - Using SystemVerilog for ASIC and FPGA Design (Paperback) Loot Price: R2,461
Discovery Miles 24 610
Repayment Terms: R231 pm x 12*
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RTL Modeling with SystemVerilog for Simulation and Synthesis - Using SystemVerilog for ASIC and FPGA Design (Paperback): Stuart...

RTL Modeling with SystemVerilog for Simulation and Synthesis - Using SystemVerilog for ASIC and FPGA Design (Paperback)

Stuart Sutherland

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Loot Price R2,461 Discovery Miles 24 610 | Repayment Terms: R231 pm x 12*

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General

Imprint: Createspace Independent Publishing Platform
Release date: June 2017
Authors: Stuart Sutherland
Dimensions: 229 x 152 x 25mm (L x W x T)
Format: Paperback - Trade
Pages: 488
ISBN-13: 978-1-5467-7634-5
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > General
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LSN: 1-5467-7634-6
Barcode: 9781546776345

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