The advancement of CMOS technologies paved the road for a growing
market of mobile and portable electronic devices. This growth is
driven by the continual integration of complex analog and digital
building blocks on a single chip, so silicon area and power
consumption are the two most valued aspects of the design. Compared
to static CMOS logic, dynamic logic offers good performance. Wide
fan-in logic such as domino circuits is used in high-performance
applications. Dynamic domino logic circuits are widely used in
modern digital VLSI circuits. These dynamic circuits are often
favored in high performance designs because of the speed advantage
offered over static CMOS logic circuits. In this dissertation, 2:1
multiplexer and 1:2 decoder is proposed. The proposed 2:1
multiplexer and 1:2 decoder design based on proposed high
performance domino logic circuit are tested in 45nm and 65nm
technologies to prove its technology independence. Design is also
experimented under various substrate-biasing schemes and then the
best substrate biasing technique is implemented. The proposed
design is better in terms of power, delay and power delay product
in comparison to other biasing conditions.
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