Transactional Memory, Second Edition (Paperback)

The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, way to coordinate concurrent threads. The ACI (atomicity, consistency, isolation) properties of transactions provide a foundation to ensure that concurrent reads and writes of shared data do not produce inconsistent or incorrect results. At a higher level, a computation wrapped in a transaction executes atomically - either it completes successfully and commits its result in its entirety or it aborts. In addition, isolation ensures the transaction produces the same result as if no other transactions were executing concurrently. Although transactions are not a parallel programming panacea, they shift much of the burden of synchronizing and coordinating parallel computations from a programmer to a compiler, to a language runtime system, or to hardware. The challenge for the system implementers is to build an efficient transactional memory infrastructure. This book presents an overview of the state of the art in the design and implementation of transactional memory systems, as of early spring 2010. Table of Contents: Introduction / Basic Transactions / Building on Basic Transactions / Software Transactional Memory / Hardware-Supported Transactional Memory / Conclusions

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Series:	Synthesis Lectures on Computer Architecture
Release date:	June 2010
First published:	2010
Authors:	Tim Harris • James Larus • Ravi Rajwar
Dimensions:	235 x 191mm (L x W)
Format:	Paperback
Pages:	247
ISBN-13:	978-3-03-100600-5
Languages:	English
Subtitles:	English
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Promotions
LSN:	3-03-100600-3
Barcode:	9783031006005

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