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Low Power Design in Deep Submicron Electronics (Hardcover, 1997 ed.)
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Low Power Design in Deep Submicron Electronics (Hardcover, 1997 ed.)
Series: NATO Science Series E:, 337
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Decreasing power dissipation per logic function has become a
primary concern in virtually all CMOS system chips designed today
as a result of the relentless progress in processing technology
that has led us into the deep-submicron age. Evolution from 1
micron to 0.1 micron lithography in the next decade will not be
possible without a change in the way we design CMOS systems. But
power reduction requires an overall optimisation, ranging from
software compilation over instruction set design down to the
introduction of much more parallelism in the architecture, the
optimal use of memory hierarchy, new clocking strategies, use of
asynchronous techniques, new CMOS circuit techniques and management
of leakage currents in new low power technologies. Moreover,
performance and power dissipation will come to be dominated by
interconnect and thus completely new floor planning and place and
route strategies are emerging. The chapters in this book present a
systematic coverage of deep submicron CMOS digital system design
for low power, from process technology all the way up to software
design and embedded software systems. Audience: An excellent guide
for the practising engineer, researcher and student interested in
this crucial aspect of actual CMOS design.
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