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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > Parallel processing

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Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design (Hardcover, 2015 ed.) Loot Price: R3,059
Discovery Miles 30 590
You Save: R485 (14%)
Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design (Hardcover, 2015 ed.): Weiwei Chen

Out-of-order Parallel Discrete Event Simulation for Electronic System-level Design (Hardcover, 2015 ed.)

Weiwei Chen

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List price R3,544 Loot Price R3,059 Discovery Miles 30 590 | Repayment Terms: R287 pm x 12* You Save R485 (14%)

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This book offers readers a set of new approaches and tools a set of tools and techniques for facing challenges in parallelization with design of embedded systems. It provides an advanced parallel simulation infrastructure for efficient and effective system-level model validation and development so as to build better products in less time. Since parallel discrete event simulation (PDES) has the potential to exploit the underlying parallel computational capability in today's multi-core simulation hosts, the author begins by reviewing the parallelization of discrete event simulation, identifying problems and solutions. She then describes out-of-order parallel discrete event simulation (OoO PDES), a novel approach for efficient validation of system-level designs by aggressively exploiting the parallel capabilities of todays' multi-core PCs. This approach enables readers to design simulators that can fully exploit the parallel processing capability of the multi-core system to achieve fast speed simulation, without loss of simulation and timing accuracy. Based on this parallel simulation infrastructure, the author further describes automatic approaches that help the designer quickly to narrow down the debugging targets in faulty ESL models with parallelism.

General

Imprint: Springer International Publishing AG
Country of origin: Switzerland
Release date: August 2014
First published: 2015
Authors: Weiwei Chen
Dimensions: 235 x 155 x 11mm (L x W x T)
Format: Hardcover
Pages: 145
Edition: 2015 ed.
ISBN-13: 978-3-319-08752-8
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > Parallel processing
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LSN: 3-319-08752-5
Barcode: 9783319087528

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