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Learning from VLSI Design Experience (Hardcover, 1st ed. 2019)
Loot Price: R3,648
Discovery Miles 36 480
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Learning from VLSI Design Experience (Hardcover, 1st ed. 2019)
Expected to ship within 10 - 15 working days
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This book shares with readers practical design knowledge gained
from the author's 24 years of IC design experience. The author
addresses issues and challenges faced commonly by IC designers,
along with solutions and workarounds. Guidelines are described for
tackling issues such as clock domain crossing, using lockup latch
to cross clock domains during scan shift, implementation of scan
chains across power domain, optimization methods to improve timing,
how standard cell libraries can aid in synthesis optimization, BKM
(best known method) for RTL coding, test compression, memory BIST,
usage of signed Verilog for design requiring +ve and -ve
calculations, state machine, code coverage and much more. Numerous
figures and examples are provided to aid the reader in
understanding the issues and their workarounds.
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