High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip (Paperback, Softcover reprint of the original 1st ed. 2018)

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

General

Imprint:	Springer Verlag, Singapore
Country of origin:	Singapore
Series:	Computer Architecture and Design Methodologies
Release date:	May 2018
First published:	2018
Authors:	Zheng Wang • Anupam Chattopadhyay
Dimensions:	235 x 155mm (L x W)
Format:	Paperback
Pages:	197
Edition:	Softcover reprint of the original 1st ed. 2018
ISBN-13:	978-981-10-9321-0
Categories:	Books > Computing & IT > General theory of computing > Systems analysis & design Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN:	981-10-9321-0
Barcode:	9789811093210

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