Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques. Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low-level faults. Hardware redundancy can be used to manage errors at the hardware architecture layer. Eventually, software implemented error detection and correction mechanisms can manage those errors that escaped the lower layers of the stack. This book presents state-of-the-art solutions for increasing the resilience of computing systems, both at single levels of abstraction and multi-layers. The book begins by addressing design techniques to improve the resilience of computing systems, covering the logic layer, the architectural layer and the software layer. The second part of the book focuses on cross-layer resilience, including coverage of physical stress, reliability assessment approaches, fault injection at the ISA level, analytical modelling for cross-later resiliency, and stochastic methods. Cross-Layer Reliability of Computing Systems is a valuable resource for researchers, postgraduate students and professional computer architects focusing on the dependability of computing systems.

Today's integrated silicon circuits and systems for wireless communications are of a huge complexity.This unique compendium covers all the steps (from the system-level to the transistor-level) necessary to design, model, verify, implement, and test a silicon system. It bridges the gap between the system-world and the transistor-world (between communication, system, circuit, device, and test engineers).It is extremely important nowadays (and will be more important in the future) for communication, system, and circuit engineers to understand the physical implications of system and circuit solutions based on hardware/software co-design as well as for device and test engineers to cope with the system and circuit requirements in terms of power, speed, and data throughput.Related Link(s)

Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults," are not covered by classical test solutions and require the dedicated test sequences presented in this book.

This book serves as a single-source reference to the latest advances in Approximate Computing (AxC), a promising technique for increasing performance or reducing the cost and power consumption of a computing system. The authors discuss the different AxC design and validation techniques, and their integration. They also describe real AxC applications, spanning from mobile to high performance computing and also safety-critical applications.

This book serves as a single-source reference to the latest advances in Approximate Computing (AxC), a promising technique for increasing performance or reducing the cost and power consumption of a computing system. The authors discuss the different AxC design and validation techniques, and their integration. They also describe real AxC applications, spanning from mobile to high performance computing and also safety-critical applications.  

Modern electronics depend on nanoscaled technologies that present new challenges in terms of testing and diagnostics. Memories are particularly prone to defects since they exploit the technology limits to get the highest density. This book is an invaluable guide to the testing and diagnostics of the latest generation of SRAM, one of the most widely applied types of memory. Classical methods for testing memory are designed to handle the so-called "static faults," but these test solutions are not sufficient for faults that are emerging in the latest Very Deep Sub-Micron (VDSM) technologies. These new fault models, referred to as "dynamic faults", are not covered by classical test solutions and require the dedicated test sequences presented in this book.