Hardware Design and Petri Nets presents a summary of the state of the art in the applications of Petri nets to designing digital systems and circuits. The area of hardware design has traditionally been a fertile field for research in concurrency and Petri nets. Many new ideas about modelling and analysis of concurrent systems, and Petri nets in particular, originated in theory of asynchronous digital circuits. Similarly, the theory and practice of digital circuit design have always recognized Petri nets as a powerful and easy-to-understand modelling tool. The ever-growing demand in the electronic industry for design automation to build various types of computer-based systems creates many opportunities for Petri nets to establish their role of a formal backbone in future tools for constructing systems that are increasingly becoming distributed, concurrent and asynchronous. Petri nets have already proved very effective in supporting algorithms for solving key problems in synthesis of hardware control circuits. However, since the front end to any realistic design flow in the future is likely to rely on more pragmatic Hardware Description Languages (HDLs), such as VHDL and Verilog, it is crucial that Petri nets are well interfaced to such languages. Hardware Design and Petri Nets is divided into five parts, which cover aspects of behavioral modelling, analysis and verification, synthesis from Petri nets and STGs, design environments based on high-level Petri nets and HDLs, and finally performance analysis using Petri nets. Hardware Design and Petri Nets serves as an excellent reference source and may be used as a text for advanced courses on the subject.

This book is devoted to logic synthesis and design techniques for asynchronous circuits. It uses the mathematical theory of Petri Nets and asynchronous automata to develop practical algorithms implemented in a public domain CAD tool. Asynchronous circuits have so far been designed mostly by hand, and are thus much less common than their synchronous counterparts, which have enjoyed a high level of design automation since the mid-1970s. Asynchronous circuits, on the other hand, can be very useful to tackle clock distribution, modularity, power dissipation and electro-magnetic interference in digital integrated circuits. This book provides the foundation needed for CAD-assisted design of such circuits, and can also be used as the basis for a graduate course on logic design.

These Transactions publish archival papers in the broad area of Petri nets and other models of concurrency, ranging from theoretical work to tool support and industrial applications. ToPNoC issues are published as LNCS volumes, and hence are widely distributed and indexed. This Journal has its own Editorial Board which selects papers based on a rigorous two-stage refereeing process. ToPNoC contains: - Revised versions of a selection of the best papers from workshops and tutorials at the annual Petri net conferences - Special sections/issues within particular subareas (similar to those published in the Advances in Petri Nets series) - Other papers invited for publication in ToPNoC - Papers submitted directly to ToPNoC by their authors The 9th volume of ToPNoC contains revised and extended versions of a selection of the best workshop papers presented at the 34th International Conference on Application and Theory of Petri Nets and Concurrency (Petri Nets 2013) and the 13th International Conference on Application of Concurrency to System Design (ACSD 2013). It also contains one paper submitted directly to ToPNoC. The 8 papers cover a diverse range of topics including model checking and system verification, refinement and synthesis, foundational work on specific classes of Petri nets, and innovative applications of Petri nets and other models of concurrency. Application areas covered in this volume are: biological systems, communication protocols, business processes, distributed systems, and multi-agent systems. Thus, this volume gives a good view of ongoing concurrent systems and Petri nets research.

This book is the result of a long friendship, of a broad international co operation, and of a bold dream. It is the summary of work carried out by the authors, and several other wonderful people, during more than 15 years, across 3 continents, in the course of countless meetings, workshops and discus sions. It shows that neither language nor distance can be an obstacle to close scientific cooperation, when there is unity of goals and true collaboration. When we started, we had very different approaches to handling the mys terious, almost magical world of asynchronous circuits. Some were more theo retical, some were closer to physical reality, some were driven mostly by design needs. In the end, we all shared the same belief that true Electronic Design Automation research must be solidly grounded in formal models, practically minded to avoid excessive complexity, and tested "in the field" in the form of experimental tools. The results are this book, and the CAD tool petrify. The latter can be downloaded and tried by anybody bold (or desperate) enough to tread into the clockless (but not lawless) domain of small-scale asynchronicity. The URL is http: //www.lsi. upc. esr j ordic/petrify. We believe that asynchronous circuits are a wonderful object, that aban dons some of the almost militaristic law and order that governs synchronous circuits, to improve in terms of simplicity, energy efficiency and performance."

The 8th volume of ToPNoC contains revised and extended versions of a selection of the best workshop papers presented at the 33rd International Conference on Application and Theory of Petri Nets and Other Models of Concurrency (Petri Nets 2012). The 10 papers cover a diverse range of topics including model checking and system verification, refinement and synthesis, foundational work on specific classes of Petri nets, and innovative applications of Petri nets and other models of concurrency. Application areas covered in this volume are: biological systems, communication protocols, business processes, collaborative team work, and Petri net education. Thus this volume gives a good view of ongoing concurrent systems and Petri nets research.

This book constitutes the refereed proceedings of the 22nd International Conference on Integrated Circuit and System Design, PATMOS 2012, held in Newcastle, UK Spain, in September 2012. The 25 revised full papers presented were carefully reviewed and selected from numerous submissions. The paper feature emerging challenges in methodologies and tools for the design of upcoming generations of integrated circuits and systems, including reconfigurable hardware such as FPGAs. The technical program focus on timing, performance and power consumption as well as architectural aspects with particular emphasis on modeling, design, characterization, analysis and optimization.

Hardware Design and Petri Nets presents a summary of the state of the art in the applications of Petri nets to designing digital systems and circuits. The area of hardware design has traditionally been a fertile field for research in concurrency and Petri nets. Many new ideas about modelling and analysis of concurrent systems, and Petri nets in particular, originated in theory of asynchronous digital circuits. Similarly, the theory and practice of digital circuit design have always recognized Petri nets as a powerful and easy-to-understand modelling tool. The ever-growing demand in the electronic industry for design automation to build various types of computer-based systems creates many opportunities for Petri nets to establish their role of a formal backbone in future tools for constructing systems that are increasingly becoming distributed, concurrent and asynchronous. Petri nets have already proved very effective in supporting algorithms for solving key problems in synthesis of hardware control circuits. However, since the front end to any realistic design flow in the future is likely to rely on more pragmatic Hardware Description Languages (HDLs), such as VHDL and Verilog, it is crucial that Petri nets are well interfaced to such languages. Hardware Design and Petri Nets is divided into five parts, which cover aspects of behavioral modelling, analysis and verification, synthesis from Petri nets and STGs, design environments based on high-level Petri nets and HDLs, and finally performance analysis using Petri nets. Hardware Design and Petri Nets serves as an excellent reference source and may be used as a text for advanced courses on the subject.

This book constitutes the refereed proceedings of the 28th International Conference on Applications and Theory of Petri Nets and Other Models of Concurrency, ICATPN 2007, held in Siedlce, Poland, in June 2007.

The 22 revised full papers and 3 revised tool papers presented together with 5 invited papers were carefully reviewed and selected from a total of 70 submissions. All current issues on research and development in the area of Petri nets and modeling of concurrent systems are addressed, in particular system design and verification, analysis, synthesis, structure and behaviour of nets, net theory and relations, causality/partial order theory of concurrency, semantic Web, logical and algebraic calculi, symbolic net representation, tools for nets, experience reports and case studies, educational issues, higher-level net models, timed and stochastic nets, as well as standardization of nets.

This LNCS State-of-the-Art Survey is devoted to the relatively old and well-known behavioral paradigm in computing, concurrency, and to the ways in which concurrency is exhibited or can be exploited in digital hardware devices.The nine chapters presented are organized in four parts on formal methods, asynchronous circuits, embedded systems design, and timed verification and performance analysis.