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Case-Based Reasoning Research and Development - 24th International Conference, ICCBR 2016, Atlanta, GA, USA, October 31 -... Case-Based Reasoning Research and Development - 24th International Conference, ICCBR 2016, Atlanta, GA, USA, October 31 - November 2, 2016, Proceedings (Paperback, 1st ed. 2016)
Ashok Goel, M Belen Diaz-Agudo, Thomas Roth-Berghofer
R2,738 Discovery Miles 27 380 Ships in 10 - 15 working days

This book constitutes the refereed proceedings of the 24th International Conference on Case-Based Reasoning Research and Development, ICCBR 2016, held in Atlanta, GA, USA, in October/November 2016. The 14 revised full papers presented were carefully reviewed and selected from 44 submissions. The papers cover a wide range of CBR topics that are of interest both to researchers and practitioners from foundations of Case-Based Reasoning; over CBR systems for specific tasks and related fields; up to CBR systems, applications and lessons learned in specific areas of expertise such as health; e-science; finance; energy, logistics, traffic; game/AI; cooking; diagnosis, technical support; as well as knowledge and experience management.

B. Arch. NATA - Self Study Guide (Paperback): Ashok Goel B. Arch. NATA - Self Study Guide (Paperback)
Ashok Goel
R960 Discovery Miles 9 600 Ships in 10 - 15 working days
B. Arch. NATA Knowledge Bank Practice Test Papers (Paperback): Ashok Goel B. Arch. NATA Knowledge Bank Practice Test Papers (Paperback)
Ashok Goel
R644 Discovery Miles 6 440 Ships in 10 - 15 working days
A One-Semester Course in Modeling of VSLI Interconnections (Paperback): Ashok Goel A One-Semester Course in Modeling of VSLI Interconnections (Paperback)
Ashok Goel
R1,843 R1,435 Discovery Miles 14 350 Save R408 (22%) Ships in 10 - 15 working days

Quantitative understanding of the parasitic capacitances and inductances, and the resultant propagation delays and crosstalk phenomena associated with the metallic interconnections on the very large scale integrated (VLSI) circuits has become extremely important for the optimum design of the state-of-the-art integrated circuits. More than 65 percent of the delays on the integrated circuit chip occur in the interconnections and not in the transistors on the chip. Mathematical techniques to model the parasitic capacitances, inductances, propagation delays, crosstalk noise, and electromigration-induced failure associated with the interconnections in the realistic high-density environment on a chip will be discussed. A One-Semester Course in Modeling of VLSI Interconnections also includes an overview of the future interconnection technologies for the nanotechnology circuits.

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