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This is the first book to focus on the problem of ensuring the
correctness of floating-point hardware designs through mathematical
methods. Formal Verification of Floating-Point Hardware Design,
Second Edition advances a verification methodology based on a
unified theory of register-transfer logic and floating-point
arithmetic that has been developed and applied to the formal
verification of commercial floating-point units over the course of
more than two decades, during which the author was employed by
several major microprocessor design companies. The theory is
extended to the analysis of several algorithms and optimization
techniques that are commonly used in commercial implementations of
elementary arithmetic operations. As a basis for the formal
verification of such implementations, high-level specifications of
the basic arithmetic instructions of several major
industry-standard floating-point architectures are presented,
including all details pertaining to the handling of exceptional
conditions. The methodology is illustrated in the comprehensive
verification of a variety of state-of-the-art commercial
floating-point designs developed by Arm Holdings. This revised
edition reflects the evolving microarchitectures and increasing
sophistication of Arm processors, and the variation in the design
goals of execution speed, hardware area requirements, and power
consumption. Many new results have been added to Parts I-III
(Register-Transfer Logic, Floating-Point Arithmetic, and
Implementation of Elementary Operations), extending the theory and
describing new techniques. These were derived as required in the
verification of the new RTL designs described in Part V.
This is the first book to focus on the problem of ensuring the
correctness of floating-point hardware designs through mathematical
methods. Formal Verification of Floating-Point Hardware Design
advances a verification methodology based on a unified theory of
register-transfer logic and floating-point arithmetic that has been
developed and applied to the formal verification of commercial
floating-point units over the course of more than two decades,
during which the author was employed by several major
microprocessor design companies. The book consists of five parts,
the first two of which present a rigorous exposition of the general
theory based on the first principles of arithmetic. Part I covers
bit vectors and the bit manipulation primitives, integer and
fixed-point encodings, and bit-wise logical operations. Part II
addresses the properties of floating-point numbers, the formats in
which they are encoded as bit vectors, and the various modes of
floating-point rounding. In Part III, the theory is extended to the
analysis of several algorithms and optimization techniques that are
commonly used in commercial implementations of elementary
arithmetic operations. As a basis for the formal verification of
such implementations, Part IV contains high-level specifications of
correctness of the basic arithmetic instructions of several major
industry-standard floating-point architectures, including all
details pertaining to the handling of exceptional conditions. Part
V illustrates the methodology, applying the preceding theory to the
comprehensive verification of a state-of-the-art commercial
floating-point unit. All of these results have been formalized in
the logic of the ACL2 theorem prover and mechanically checked to
ensure their correctness. They are presented here, however, in
simple conventional mathematical notation. The book presupposes no
familiarity with ACL2, logic design, or any mathematics beyond
basic high school algebra. It will be of interest to verification
engineers as well as arithmetic circuit designers who appreciate
the value of a rigorous approach to their art, and is suitable as a
graduate text in computer arithmetic.
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