Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.

This invaluable textbook covers the theory and circuit design techniques to implement CMOS (Complementary Metal-Oxide Semiconductor) class-D audio amplifiers integrated circuits. The first part of the book introduces the motivation and fundamentals of audio amplification. The loudspeaker's operation and main audio performance metrics explains the limitations in the amplification process. The second part of this book presents the operating principle and design procedure of the class-D amplifier main architectures to provide the performance tradeoffs. The circuit design procedures involved in each block of the class-D amplifier architecture are highlighted. The third part of this book discusses several important design examples introducing state-of-the-art architectures and circuit design techniques to improve the audio performance, power consumption, and efficiency of standard class-D audio amplifiers.

This invaluable textbook covers the theory and circuit design techniques to implement CMOS (Complementary Metal-Oxide Semiconductor) class-D audio amplifiers integrated circuits. The first part of the book introduces the motivation and fundamentals of audio amplification. The loudspeaker's operation and main audio performance metrics explains the limitations in the amplification process. The second part of this book presents the operating principle and design procedure of the class-D amplifier main architectures to provide the performance tradeoffs. The circuit design procedures involved in each block of the class-D amplifier architecture are highlighted. The third part of this book discusses several important design examples introducing state-of-the-art architectures and circuit design techniques to improve the audio performance, power consumption, and efficiency of standard class-D audio amplifiers.

Thanks to the advance of semiconductor and communication technology, the wireless communication market has been booming in the last two decades. It evolved from simple pagers to emerging third-generation (3G) cellular phones. In the meanwhile, broadband communication market has also gained a rapid growth. As the market always demands hi- performance and low-cost products, circuit designers are seeking hi- integration communication devices in cheap CMOS technology. The phase-locked loop frequency synthesizer is a critical component in communication devices. It works as a local oscillator for frequency translation and channel selection in wireless transceivers and broadband cable tuners. It also plays an important role as the clock synthesizer for data converters in the analog-and-digital signal interface. This book covers the design and analysis of PLL synthesizers. It includes both fundamentals and a review of the state-of-the-art techniques. The transient analysis of the third-order charge-pump PLL reveals its locking behavior accurately. The behavioral-level simulation of PLL further clarifies its stability limit. Design examples are given to clearly illustrate the design procedure of PLL synthesizers. A complete derivation of reference spurs in the charge-pump PLL is also presented in this book. The in-depth investigation of the digital CA modulator for fractional-N synthesizers provides insightful design guidelines for this important block.

The wireless communication systems have become an important part of our lives. The ever increasing demand toward lower cost makes the task of the wireless communication circuit designer more and more challenging. This demand translates into the specifications as the need of designing the circuits with lower power consumption, with smaller die area but without any compromise from the final goal of higher performance. The circuit design for wireless transceiver front-ends has an additional complexity due to the high frequency of operation involved. This book includes discussions on the fully-integrated VCOs, prescalers and Q-enhanced LC bandpass filters on silicon within the framework of RF integrated circuit design for wireless communication transceivers. The advantages and shortcomings of the circuits are presented together with the associated design trade-offs, based on simplified noise and nonlinearity analyses. Measurement results of the designed and implemented LC VCOs, a dual-modulus prescaler and a Q-enhanced LC bandpass filter are provided. This book will be of interest to analog circuit designers and researchers in the field of RF IC design.