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This book provides a comprehensive introduction to hardware
security, from specification to implementation. Applications
discussed include embedded systems ranging from small RFID tags to
satellites orbiting the earth. The authors describe a design and
synthesis flow, which will transform a given circuit into a secure
design incorporating counter-measures against fault attacks. In
order to address the conflict between testability and security, the
authors describe innovative design-for-testability (DFT)
computer-aided design (CAD) tools that support security challenges,
engineered for compliance with existing, commercial tools. Secure
protocols are discussed, which protect access to necessary test
infrastructures and enable the design of secure access controllers.
This book provides a comprehensive introduction to hardware
security, from specification to implementation. Applications
discussed include embedded systems ranging from small RFID tags to
satellites orbiting the earth. The authors describe a design and
synthesis flow, which will transform a given circuit into a secure
design incorporating counter-measures against fault attacks. In
order to address the conflict between testability and security, the
authors describe innovative design-for-testability (DFT)
computer-aided design (CAD) tools that support security challenges,
engineered for compliance with existing, commercial tools. Secure
protocols are discussed, which protect access to necessary test
infrastructures and enable the design of secure access controllers.
This book constitutes revised selected papers from the 11th
International Workshop on Constructive Side-Channel Analysis and
Secure Design, COSADE 2020, held in Lugano, Switzerland, in April
2020. Due to COVID-19, the workshop was held online. The 15 papers
presented in this volume were carefully reviewed and selected from
36 submissions. The workshop covers subjects from wide ranges such
as secure design, side channel attacks and countermeasures, and
architectures and protocols.
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