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Proceedings of the 3rd International Conference on Communication, Devices and Computing - ICCDC 2021 (Hardcover, 1st ed. 2022):... Proceedings of the 3rd International Conference on Communication, Devices and Computing - ICCDC 2021 (Hardcover, 1st ed. 2022)
Biplab Sikdar, Santi Prasad Maity, Jagannath Samanta, Avisankar Roy
R7,042 Discovery Miles 70 420 Ships in 10 - 15 working days

This book provides insights into the 3rd International Conference on Communication, Devices and Computing (ICCDC 2021), which was held in Haldia, India, on August 16-18, 2021. It covers new ideas, applications, and the experiences of research engineers, scientists, industrialists, scholars, and students from around the globe. The proceedings highlight cutting-edge research on communication, electronic devices, and computing and address diverse areas such as 5G communication, spread spectrum systems, wireless sensor networks, and signal processing for secure communication, error control coding, printed antennas, analysis of wireless networks, antenna array systems, analog and digital signal processing for communication systems, frequency selective surfaces, radar communication, and substrate integrated waveguide and microwave passive components, which are key to state-of-the-art innovations in communication technologies.

UDSM CMOS Circuits (Paperback): Jagannath Samanta UDSM CMOS Circuits (Paperback)
Jagannath Samanta
R1,354 Discovery Miles 13 540 Ships in 10 - 15 working days

A simple and accurate delay model is proposed for Ultra Deep Sub-micron CMOS circuits (CMOS Inverter, NAND2, NOR2 etc) based on nth power law when the channel length is less than the 90nm. All the parameters are taken from BSIM.4.6.1 manual. This work derives analytical expression for the delay model of a CMOS inverter including all sorts of secondary effects i.e. Body Bias effect, Channel Length Modulation Effect (CLM), Velocity Saturation effect, Drain Induced Barrier Lowering (DIBL), Gate Induced Drain Leakage (GIDL), Substrate Current Induced Body Effect (SCBE), Drain-Induced Threshold Shift (DITS), which may occur in the Ultra Deep Submicron MOS devices. We also extend our delay model for 2 inputs CMOS NAND & NOR gates. Our result is better than simulation result with respect to both quality and estimation time. This work also thoroughly described the delay dependence on different parameters such as channel length, Load Capacitance, Supply voltage, Transition time, Velocity Saturation Coefficient, Threshold Voltage, Load Resistance, Width variation etc. This also explained the different power models for the estimation of UDSM circuts.

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