Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems. Efficient algorithms are given for tractable covering problems and general techniques are given for dealing with a large number of intractable covering problems. The book begins with an investigation of algorithms for the reconfiguration of large redundant memories. Next, a number of more general covering problems are considered and the complexity of these problems is analyzed. Finally, a general and uniform approach is proposed for solving a wide class of covering problems. The results and techniques described here will be useful to researchers and students working in this area. As such, the book serves as an excellent reference and may be used as the text for an advanced course on the topic.

We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore's law. This observation stated that transistor density in integrated circuits doubles every 1. 5-2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore's law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

In the last few decades, multiscale algorithms have become a dominant trend in large-scale scientific computation. Researchers have successfully applied these methods to a wide range of simulation and optimization problems. This book gives a general overview of multiscale algorithms; applications to general combinatorial optimization problems such as graph partitioning and the traveling salesman problem; and VLSICAD applications, including circuit partitioning, placement, and VLSI routing. Additional chapters discuss optimization in reconfigurable computing, convergence in multilevel optimization, and model problems with PDE constraints.

Audience Written at the graduate level, the book is intended for engineers and mathematical and computational scientists studying large-scale optimization in electronic design automation.

This book covers advanced techniques in modern circuit placement. It details all of most recent placement techniques available in the field and analyzes the optimality of these techniques. Coverage includes all the academic placement tools that competed against one another on the same industrial benchmark circuits at the International Symposium on Physical Design (ISPD), these techniques are also extensively being used in industrial tools as well. The book provides significant amounts of analysis on each technique such as trade-offs between quality-of-results (QoR) and runtime.

In the last few decades, multiscale algorithms have become a dominant trend in large-scale scientific computation. Researchers have successfully applied these methods to a wide range of simulation and optimization problems. This book gives a general overview of multiscale algorithms; applications to general combinatorial optimization problems such as graph partitioning and the traveling salesman problem; and VLSICAD applications, including circuit partitioning, placement, and VLSI routing. Additional chapters discuss optimization in reconfigurable computing, convergence in multilevel optimization, and model problems with PDE constraints.

Audience Written at the graduate level, the book is intended for engineers and mathematical and computational scientists studying large-scale optimization in electronic design automation.

Fault Covering Problems in Reconfigurable VLSI Systems describes the authors' recent research on reconfiguration problems for fault-tolerance in VLSI and WSI Systems. The book examines solutions to a number of reconfiguration problems. Efficient algorithms are given for tractable covering problems and general techniques are given for dealing with a large number of intractable covering problems. The book begins with an investigation of algorithms for the reconfiguration of large redundant memories. Next, a number of more general covering problems are considered and the complexity of these problems is analyzed. Finally, a general and uniform approach is proposed for solving a wide class of covering problems. The results and techniques described here will be useful to researchers and students working in this area. As such, the book serves as an excellent reference and may be used as the text for an advanced course on the topic.

This book covers advanced techniques in modern circuit placement. It details all of most recent placement techniques available in the field and analyzes the optimality of these techniques. Coverage includes all the academic placement tools that competed against one another on the same industrial benchmark circuits at the International Symposium on Physical Design (ISPD), these techniques are also extensively being used in industrial tools as well. The book provides significant amounts of analysis on each technique such as trade-offs between quality-of-results (QoR) and runtime.

We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore's law. This observation stated that transistor density in integrated circuits doubles every 1. 5-2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore's law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).