This book gathers outstanding research papers presented in the International Conference on Computational Intelligence and Emerging Power System (ICCIPS 2021), held on March 9-10, 2021, at Engineering College Ajmer. ICCIPS 2021 is jointly organized by the Department of CSE and Department of EE, Engineering College Ajmer, Rajasthan, India. The topics covered in the book are collective intelligence, soft computing, optimization, cloud computing, machine learning, intelligent software, robotics, data science, data security, big data analytics, natural language processing, renewable energy, signal processing, optimization methods for power system, smart grid, micro-grid, energy management, power system, monitoring system, load management, and distributed generation.

This book gathers outstanding research papers presented in the International Conference on Computational Intelligence and Emerging Power System (ICCIPS 2021), held on March 9-10, 2021, at Engineering College Ajmer. ICCIPS 2021 is jointly organized by the Department of CSE and Department of EE, Engineering College Ajmer, Rajasthan, India. The topics covered in the book are collective intelligence, soft computing, optimization, cloud computing, machine learning, intelligent software, robotics, data science, data security, big data analytics, natural language processing, renewable energy, signal processing, optimization methods for power system, smart grid, micro-grid, energy management, power system, monitoring system, load management, and distributed generation.

In recent years, low power design has become one of the prime focuses for digital VLSI circuits. As technology scales down, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book is based on pre-layout and post-layout simulations of a modified 9T full adder and 9T full adder circuit in subthreshold as well as super threshold region. The 9T circuit consists of a new logic, which is used to implement Sum module. This design remarkably reduces power consumption hence improves power-delay product (PDP) and temperature sustainability along with noise immunity and threshold loss when compared with the modified 8T adder. This book, therefore, provides a new metric of implementing high performance full adder circuit. This analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field.

Arithmetic circuits, like adders and multipliers, are one of the basic components in the design of communication circuits. In fact 8.72% of all instructions in a typical scientific program are multiplies. The multiplier is a fairly large block of a computing system. Multiplier is not only a high-delay block but also a significant source of power dissipation. That's why, if one also aims to minimize power consumption, it is of great interest to identify the techniques to be applied to reduce delay by using various delay optimizations. Array architecture is a popular technique to implement the multipliers due to its compact structure. In this book, six array multiplier circuits using different AND cells and XOR gates have been designed, simulated, analyzed and compared. This analysis should help shed some light on the low power and high throughput 2x2 array multiplier cells and should be especially useful for post graduate students and research scholars working in low power VLSI circuit design field."

Full adder is an essential component for designing all types of processors viz. digital signal processors (DSP), microprocessors etc. In most of the digital systems adder lies in the critical path that affects the overall speed of the system. So enhancing the performance of the 1-bit full adder cell is of prime concern. This book presents the general methodology to modify performance of full adder by adding an extra transistor to the node causing loss. The introduced design of full adder cell remarkably reduces power consumption hence PDP, improves noise immunity and temperature sustainability in comparison to the conventional design. All simulations are performed on 45nm and 90nm standard models on Tanned EDA tool version 12.6. This book, therefore, provides a new metric of implementing high performance technology independent full adder circuit and the Ripple Carry Adder as its application. The analysis should help shed some light on the new and exciting approach for achieving low power and high throughput adder cell and should be especially useful to post graduate students and research scholars in VLSI circuit design field.