In recent years, low power design has become one of the focuses of digital VLSI circuits. As technology scales, leakage currents in contemporary CMOS logic have become one of the main power consumers. Contrary to conventional methods for power reduction, operation of digital circuits in the subthreshold region minimizes power consumption in low-frequency systems. This book presents pre-layout and post-layout simulations of existing 8T Latch and proposed latch designs in sub-threshold region. The proposed circuits consist of pass transistor gate logic. Proposed designs are area efficient so useful for portable devices. The proposed designs remarkably reduce power consumption and delay hence reduces power-delay product (PDP). Comparison with the existing design and proposed latch designs are performed at 65nm and 45nm to show technology independence. Comparative simulation results show that proposed 7T latch design with delay is better choice for portable applications. Therefore, the proposed 7T latch design with delay proves to be a viable option for low power and energy efficient applications.

The advancement of CMOS technologies paved the road for a growing market of mobile and portable electronic devices. This growth is driven by the continual integration of complex analog and digital building blocks on a single chip, so silicon area and power consumption are the two most valued aspects of the design. Compared to static CMOS logic, dynamic logic offers good performance. Wide fan-in logic such as domino circuits is used in high-performance applications. Dynamic domino logic circuits are widely used in modern digital VLSI circuits. These dynamic circuits are often favored in high performance designs because of the speed advantage offered over static CMOS logic circuits. In this dissertation, 2:1 multiplexer and 1:2 decoder is proposed. The proposed 2:1 multiplexer and 1:2 decoder design based on proposed high performance domino logic circuit are tested in 45nm and 65nm technologies to prove its technology independence. Design is also experimented under various substrate-biasing schemes and then the best substrate biasing technique is implemented. The proposed design is better in terms of power, delay and power delay product in comparison to other biasing conditions.