Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CAD EDA industry professionals, academics and students.

While there have been remarkable advances in recent years in the areas of both coding and detection for data storage, this book focuses on data detection, or the processing of reading back waveforms to reproduce stored data, in conjunction with the traditional modulation coding method called run-length-limited or (d, k) coding. Among notable recent advances in the area of data detection is the application of the Viterbi algorithm combined with partial response linear equalization, known as partial response maximum likelihood (PRML), to commercial magnetic disk drives. The decision feedback equalizer (DFE), a well established data detection technique in communication channels subject to intersymbol interference (ISI), has also attracted attention in the magnetic recording community. One of the objectives of this book is to provide a tutorial review of the application of these detection schemes to magnetic recording. Philosophies behind these detection schemes are explained, as well as methods for analyzing their performances.Performance of these detection schemes is compared with that of the traditional peak detection method to provide insight into density improvements that can be achieved using these schemes. The main emphasis of the book is on the more recent idea proposed by the authors, namely, the application of fixed delay tree search (FDTS) to high density magnetic recording. Although the idea of depth-limited tree search has long existed in coding and in detection for ISI channels, it has not been previously noted that, for certain constrained ISI channels, depth-limited tree search yields an asymptotically optimal performance. This book explores the idea of depth-limited search on constrained channels and shows how a relatively simple FDTS detector combined with DFE, called FDTS/DF, achieves a near-optimal performance when applied to high density magnetic recording where the minimum run-length constraint may be required to suppress nonlinearities and media noise.

In the early days of VLSI, the design of the power distribution for an integrated cir cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks."

Practical Synthesis of High-Performance Analog Circuits presents a technique for automating the design of analog circuits. Market competition and the astounding pace of technological innovation exert tremendous pressure on circuit design engineers to turn ideas into products quickly and get them to market. In digital Application Specific Integrated Circuit (ASIC) design, computer aided design (CAD) tools have substantially eased this pressure by automating many of the laborious steps in the design process, thereby allowing the designer to maximise his design expertise. But the world is not solely digital. Cellular telephones, magnetic disk drives, neural networks and speech recognition systems are a few of the recent technological innovations that rely on a core of analog circuitry and exploit the density and performance of mixed analog/digital ASICs. To maximize profit, these mixed-signal ASICs must also make it to market as quickly as possible. However, although the engineer working on the digital portion of the ASIC can rely on sophisticated CAD tools to automate much of the design process, there is little help for the engineer working on the analog portion of the chip. With the exception of simulators to verify the circuit design when it is complete, there are almost no general purpose CAD tools that an analog design engineer can take advantage of to automate the analog design flow and reduce his time to market. Practical Synthesis of High-Performance Analog Circuits presents a new variation-tolerant analog synthesis strategy that is a significant step towards ending the wait for a practical analog synthesis tool. A new synthesis strategy is presented that can fully automate the path from a circuit topology and performance specifications to a sized variation-tolerant circuit schematic. This strategy relies on asymptotic waveform evaluation to predict circuit performance and simulated annealing to solve a novel non-linear infinite programming optimization formulation of the circuit synthesis problem via a sequence of smaller optimization problems. Practical Synthesis of High-Performance Analog Circuits will be of interest to analog circuit designers, CAD/EDA industry professionals, academics and students.

The move to higher levels of integration has increased the fraction of application-specific integrated circuit (ASIC) designs containing both analog and digital circuits. While the die area for the analog portion of these chips is modest, the design time is often significant. This has motivated the development of automated analog physical design tools for cell-level place-and-route and system-level signal-integrity-routing. To date, there is no tool that has specifically addressed the critical design task of synthesizing the power distribution for the analog portion of an analog or mixed-signal ASIC. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs describes algorithms for analog power distribution synthesis and demonstrates their effectiveness. Existing digital power bus synthesis algorithms have failed to address critical concerns for analog circuitry, thus yielding unacceptable results. These tools synthesize only the bus component of power distribution networks and only consider simplified DC aspects of macros and busses. Readers of the companion book in this series, Simulation Techniques and Solutions for Mixed-Signal Coupling in Integrated Circuits (Kluwer Academic Publishers), already recognize the inadequacy of this simplified view of the noise and power distribution problem in mixed-signal integrated circuits. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs addresses power distribution synthesis for mixed-signal integrated circuits. Several key challenges in power distribution design are identified and automated methods to overcome them are described. This book presents a new formulation for the analog powerdistribution synthesis problem which synthesizes both the power busses power I/O cell assignment by evaluating DC, AC, and transient interaction between the macros, busses, chip substrate, and package. Furthermore, algorithms are introduced which simultaneously optimize power I/O cell assignment, macro cell substrate coupling, power bus topology selection and power bus sizing. Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs will be of interest to CAD designers and researchers specializing in physical design, modelling and circuit synthesis.

Computer-Aided Design of Analog Circuits and Systems brings together in one place important contributions and state-of-the-art research results in the rapidly advancing area of computer-aided design of analog circuits and systems. This book serves as an excellent reference, providing insights into some of the most important issues in the field.

Magnetic data storage can be viewed as a data communication system. This is not a sUlprising view, considering that data storage is essentially the transfer of data between different times. The past decade has indeed seen rapidly growing interest in applying improved coding and detection techniques to magnetic data storage, a traditional approach to enhance performance of communication channels. Since its inception in the 1930's, the magnetic recording industry has achieved impressive progress in data capacity. This has been made possible mainly by innovations and advances in heads and media design. However, as the demand for higher storage capacity continues in the modem information era, a need arises to explore other possibilities to help meet the ever-growing demand. Advanced coding and detection are one such possibility, providing an efficient, cost-effective means to increase data capacity. In fact, with the advent of modem Ie technology which has enabled real-time implementation of increasingly complex signal processing algorithms, advanced coding and detection are rapidly becoming a major issue in the development of improved data storage products. While there have been remarkable advances in recent years in the areas of both coding and detection for data storage, this book focuses only on data detection, or the processing of readback waveforms to reproduce stored data, in conjunction with the traditional modulation coding method called run length-limited or (d, k) coding."