Interconnect has become the dominating factor in determining system performance in nanometer technologies. This book is dedicated to this important subject. The primary purpose of this monograph is to provide insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits. In this monograph, the effects of wire size, spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, shields, direction of the signals, and wire width for both the aggressors and the victim wires on system performance and reliability is thoroughly investigated. Also, parameters like driver strength has been considered as several recent studies considered the simultaneous device and interconnect sizing. Crosstalk noise, as well as the impact of coupling on aggressor delay is analyzed. The pulse width of the crosstalk noise, which is of similar importance for circuit performance as the peak amplitude, is also analyzed. We have considered more parameters that can affect the signal integrity and presented a practical intensive simulation results. throughout the literature, presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. The practical aspects of the algorithms and models are explained with sufficient detail. It deeply investigates the most two effective parameters in layout optimization, spacing and shield insertion, that can affect both capacitive and inductive noise. Noise models needed for layouts with multi-layer multi-crosscoupling segments are investigated. Different post-layout optimization techniques are explained with complexity analysis and benchmarks tests are provided.

This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: * Current developments in Digital Signal Processing (DSP) pro cessors and architectures - several examples and case studies of existing DSP chips are discussed in Chapter 1. * Features and requirements of image and video signal processing architectures - both applications specific integrated circuits (ASICs) and programmable image processors are studied in Chapter 2. * New market areas for signal processing - especially in consumer electronics such as multimedia, teleconferencing, and movie on demand. * Impact of arithmetic circuitry on the performance of DSP pro cessors - several topics are discussed in Chapter 3 such as: number representation, arithmetic algorithms and circuits, and implementa tion.

Learning on Silicon combines models of adaptive information processing in the brain with advances in microelectronics technology and circuit design. The premise is to construct integrated systems not only loaded with sufficient computational power to handle demanding signal processing tasks in sensory perception and pattern recognition, but also capable of operating autonomously and robustly in unpredictable environments through mechanisms of adaptation and learning. This edited volume covers the spectrum of Learning on Silicon in five parts: adaptive sensory systems, neuromorphic learning, learning architectures, learning dynamics, and learning systems. The 18 chapters are documented with examples of fabricated systems, experimental results from silicon, and integrated applications ranging from adaptive optics to biomedical instrumentation. As the first comprehensive treatment on the subject, Learning on Silicon serves as a reference for beginners and experienced researchers alike. It provides excellent material for an advanced course, and a source of inspiration for continued research towards building intelligent adaptive machines.

Designing VLSI systems represents a challenging task. It is a transfonnation among different specifications corresponding to different levels of design: abstraction, behavioral, stntctural and physical. The behavioral level describes the functionality of the design. It consists of two components; static and dynamic. The static component describes operations, whereas the dynamic component describes sequencing and timing. The structural level contains infonnation about components, control and connectivity. The physical level describes the constraints that should be imposed on the floor plan, the placement of components, and the geometry of the design. Constraints of area, speed and power are also applied at this level. To implement such multilevel transfonnation, a design methodology should be devised, taking into consideration the constraints, limitations and properties of each level. The mapping process between any of these domains is non-isomorphic. A single behavioral component may be transfonned into more than one structural component. Design methodologies are the most recent evolution in the design automation era, which started off with the introduction and subsequent usage of module generation especially for regular structures such as PLA's and memories. A design methodology should offer an integrated design system rather than a set of separate unrelated routines and tools. A general outline of a desired integrated design system is as follows: * Decide on a certain unified framework for all design levels. * Derive a design method based on this framework. * Create a design environment to implement this design method.

Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac ceptable speed performance."

This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: * Current developments in Digital Signal Processing (DSP) pro cessors and architectures - several examples and case studies of existing DSP chips are discussed in Chapter 1. * Features and requirements of image and video signal processing architectures - both applications specific integrated circuits (ASICs) and programmable image processors are studied in Chapter 2. * New market areas for signal processing - especially in consumer electronics such as multimedia, teleconferencing, and movie on demand. * Impact of arithmetic circuitry on the performance of DSP pro cessors - several topics are discussed in Chapter 3 such as: number representation, arithmetic algorithms and circuits, and implementa tion.

Designing VLSI systems represents a challenging task. It is a transfonnation among different specifications corresponding to different levels of design: abstraction, behavioral, stntctural and physical. The behavioral level describes the functionality of the design. It consists of two components; static and dynamic. The static component describes operations, whereas the dynamic component describes sequencing and timing. The structural level contains infonnation about components, control and connectivity. The physical level describes the constraints that should be imposed on the floor plan, the placement of components, and the geometry of the design. Constraints of area, speed and power are also applied at this level. To implement such multilevel transfonnation, a design methodology should be devised, taking into consideration the constraints, limitations and properties of each level. The mapping process between any of these domains is non-isomorphic. A single behavioral component may be transfonned into more than one structural component. Design methodologies are the most recent evolution in the design automation era, which started off with the introduction and subsequent usage of module generation especially for regular structures such as PLA's and memories. A design methodology should offer an integrated design system rather than a set of separate unrelated routines and tools. A general outline of a desired integrated design system is as follows: * Decide on a certain unified framework for all design levels. * Derive a design method based on this framework. * Create a design environment to implement this design method.

Over the past few years, the demand for high speed Digital Signal Proces sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time. The communication between the two channels has to be minimized. 3. Applicatilm specific systems: this emerging approach should achieve real-time performance in a cost-effective way. 4. Testability and fault tolerance: reliability has become a required feature in most of DSP systems. To achieve such property, the involved time overhead is significant. Parallelism may be the solution to maintain ac ceptable speed performance."

Interconnect has become the dominating factor in determining system performance in nanometer technologies. This book is dedicated to this important subject. The primary purpose of this monograph is to provide insight and intuition into layout analysis and optimization for interconnect in high speed, high complexity integrated circuits.

In this monograph, the effects of wire size, spacing between wires, wire length, coupling length, load capacitance, rise time of the inputs, place of overlap (near driver or receiver side), frequency, shields, direction of the signals, and wire width for both the aggressors and the victim wires on system performance and reliability is thoroughly investigated. Also, parameters like driver strength has been considered as several recent studies considered the simultaneous device and interconnect sizing. Crosstalk noise, as well as the impact of coupling on aggressor delay is analyzed. The pulse width of the crosstalk noise, which is of similar importance for circuit performance as the peak amplitude, is also analyzed. We have considered more parameters that can affect the signal integrity and presented practical intensive simulation results.

This book brings together a wealth of information previously scattered throughout the literature, presenting a range of CAD algorithms and techniques for synthesizing and optimizing interconnect. The practical aspects of the algorithms and models are explained with sufficient detail.

It deeply investigates the most two effective parameters in layout optimization, spacing and shield insertion, that can affect both capacitive and inductive noise. Noise models needed for layouts with multi-layer multi-crosscoupling segments are investigated. Different post-layout optimization techniques are explained with complexity analysis and benchmarks tests are provided.