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Analysis and Design of Networks-on-Chip Under High Process Variation (Hardcover, 1st ed. 2015): Rabab Ezz-Eldin, Magdy Ali... Analysis and Design of Networks-on-Chip Under High Process Variation (Hardcover, 1st ed. 2015)
Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
R3,665 R3,299 Discovery Miles 32 990 Save R366 (10%) Ships in 12 - 17 working days

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

Transaction-Level Power Modeling (Hardcover, 1st ed. 2020): Amr Baher Darwish, Magdy Ali El-Moursy, Mohamed Amin Dessouky Transaction-Level Power Modeling (Hardcover, 1st ed. 2020)
Amr Baher Darwish, Magdy Ali El-Moursy, Mohamed Amin Dessouky
R1,469 Discovery Miles 14 690 Ships in 10 - 15 working days

This book describes for readers a methodology for dynamic power estimation, using Transaction Level Modeling (TLM). The methodology exploits the existing tools for RTL simulation, design synthesis and SystemC prototyping to provide fast and accurate power estimation using Transaction Level Power Modeling (TLPM). Readers will benefit from this innovative way of evaluating power on a high level of abstraction, at an early stage of the product life cycle, decreasing the number of the expensive design iterations.

Analysis and Design of Networks-on-Chip Under High Process Variation (Paperback, Softcover reprint of the original 1st ed.... Analysis and Design of Networks-on-Chip Under High Process Variation (Paperback, Softcover reprint of the original 1st ed. 2015)
Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed
R2,789 Discovery Miles 27 890 Ships in 10 - 15 working days

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

Transaction-Level Power Modeling (Paperback, 1st ed. 2020): Amr Baher Darwish, Magdy Ali El-Moursy, Mohamed Amin Dessouky Transaction-Level Power Modeling (Paperback, 1st ed. 2020)
Amr Baher Darwish, Magdy Ali El-Moursy, Mohamed Amin Dessouky
R1,423 Discovery Miles 14 230 Ships in 10 - 15 working days

This book describes for readers a methodology for dynamic power estimation, using Transaction Level Modeling (TLM). The methodology exploits the existing tools for RTL simulation, design synthesis and SystemC prototyping to provide fast and accurate power estimation using Transaction Level Power Modeling (TLPM). Readers will benefit from this innovative way of evaluating power on a high level of abstraction, at an early stage of the product life cycle, decreasing the number of the expensive design iterations.

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