System on Chip Interfaces for Low Power Design provides a top-down understanding of interfaces available to SoC developers, not only the underlying protocols and architecture of each, but also how they interact and the tradeoffs involved. The book offers a common context to help understand the variety of available interfaces and make sense of technology from different vendors aligned with multiple standards. With particular emphasis on power as a factor, the authors explain how each interface performs in various usage scenarios and discuss their advantages and disadvantages. Readers learn to make educated decisions on what interfaces to use when designing systems and gain insight for innovating new/custom interfaces for a subsystem and their potential impact.

Impurity profiling and drug degradation pathways are essentials features for regulatory acceptance of any new drug entity. Despite of technological advancements in pharmaceutical analysis, structural elucidation of drug molecules, impurities produced during formulation remains challenging tasks for researchers. Unique chemical behavior, complex properties and interactions of different functional groups involved in active pharmaceutical ingredients along with different chemical environments with excipients and storage condition further complicate the issues. Furthermore isolation and characterization of impurities with special references to toxic metabolites is essential for acceptance of new drug molecules by regulatory agencies. Recently discovered and patented nitrate esters of paracetamol having improved analgesic and anti-inflammatory activities then parent drug and less hepatotoxicity in overdose is selected as model drug entity. This book is an attempt to provide experimental insights into the chemical, analytical and establishment of drug degradation pathways in forced conditions in lucid manner for easy understanding to meet future expectations of scientific fraternities.

In the present work of Xilinx HDLC controller. HDLC operates at the data link layer of the OSI Model main focus of the is to understand the data link layer and develop a protocol which can offer its services to the layer above it i.e. is the network layer and the layer below it i.e. the physical layer. The function of this protocol controller is to perform a number of separate activities like physical addressing, to check for errors, flow control design of HDLC Controller and simulation design and implement a high performance. This will then be coded in a hardware description language (VHDL). The functioning of the coded design is to be simulated on simulation software (e.g. Model Sim.).After proper simulation, the design is to be synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model the design is mapped to the existing slices of the FPGA and the post-map model simulated.The objective is to run the programmed FPGA high as possible.