Variability is one of the most challenging obstacles for IC design in the nanometer regime. In nanometer technologies, SRAM show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost, while achieving higher performance and density. With the drastic increase in memory densities, lower supply voltages, and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power. This book is an invaluable reference on robust SRAM circuits and statistical design methodologies for researchers and practicing engineers in the field of memory design. It combines state of the art circuit techniques and statistical methodologies to optimize SRAM performance and yield in nanometer technologies. Provides comprehensive review of state-of-the-art, variation-tolerant SRAM circuit techniques; Discusses Impact of device related process variations and how they affect circuit and system performance, from a design point of view; Helps designers optimize memory yield, with practical statistical design methodologies and yield estimation techniques.

Since the early-1990s, reducing the dynamic switching power has been the main focus in many of the proposed low-power circuit techniques. At that time, the off-state leakage power was negligible compared to dynamic power. However, as technology scales into the deep-submicron regime, the increase in leakage power can no longer be neglected. Soon, the biggest challenge that SoC designers must resolve is the fact that transistors for digital and memory circuits will be more and more leaky as technology generations advance. The semiconductor industry must therefore reduce leakage current in chip designs by two orders of magnitude over the next ten years, or face an interruption in projected chip complexity. Failure to do so would make the mounting leakage current the big stumbling block to Moore's Law. Furthermore, co-operative approaches between computer-aided design development, circuit design, and technology process must be examined. Multi-threshold voltage CMOS (MTCMOS) technology, that has emerged as an increasingly popular technique to control the escalating leakage power, while maintaining high performance. The book addresses the leakage problem in a number of designs for combinational, sequential, dynamic, and current-steering logic. Moreover, computer-aided design methodologies for designing low-leakage integrated circuits are presented. The book give a survey of state-of-the-art techniques presented in the literature as well as proposed designs that minimize leakage power, while achieving high-performance. Multi-Threshold CMOS Digital Circuits Managing Leakage Power is written for students of VLSI design as well as practicing circuit designers, system designers, CAD tool developers and researchers. It assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit design techniques.

Variability is one of the most challenging obstacles for IC design in the nanometer regime. In nanometer technologies, SRAM show an increased sensitivity to process variations due to low-voltage operation requirements, which are aggravated by the strong demand for lower power consumption and cost, while achieving higher performance and density. With the drastic increase in memory densities, lower supply voltages, and higher variations, statistical simulation methodologies become imperative to estimate memory yield and optimize performance and power. This book is an invaluable reference on robust SRAM circuits and statistical design methodologies for researchers and practicing engineers in the field of memory design. It combines state of the art circuit techniques and statistical methodologies to optimize SRAM performance and yield in nanometer technologies. Provides comprehensive review of state-of-the-art, variation-tolerant SRAM circuit techniques; Discusses Impact of device related process variations and how they affect circuit and system performance, from a design point of view; Helps designers optimize memory yield, with practical statistical design methodologies and yield estimation techniques.

This book is an eye-opener for businesses unveiling how technology trends can be deployed to redesign products, services and processes. The authors provide business opportunities based on technological innovation across 10 industrial sectors in easy to read case studies. Each case study is a story that narrates the potential and influence of a technological innovation on an enterprise, by defining the challenges faced, the type of technology adopted, and the impact. Provides readers with compelling reasons for implementing technology trends in industrial value chains; Written in a simple, easy to read and exciting manner to be accessible to readers with different backgrounds and interests; Uses a single, structured paradigm in all the case studies.

This excellent survey of state-of-the-art techniques discusses the MTCMOS technology that has emerged as an increasingly popular technique to control the escalating leakage power, while maintaining high performance. It addresses the leakage problem in a number of designs for combinational, sequential, dynamic and current-steering logic.