This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

The microelectronics market, with special emphasis to the production of complex mixed-signal systems-on-chip (SoC), is driven by three main dynamics, time-- market, productivity and managing complexity. Pushed by the progress in na- meter technology, the design teams are facing a curve of complexity that grows exponentially, thereby slowing down the productivity design rate. Analog design automation tools are not developing at the same pace of technology, once custom design, characterized by decisions taken at each step of the analog design flow, - lies most of the time on designer knowledge and expertise. Actually, the use of - sign management platforms, like the Cadences Virtuoso platform, with a set of - tegrated CAD tools and database facilities to deal with the design transformations from the system level to the physical implementation, can significantly speed-up the design process and enhance the productivity of analog/mixed-signal integrated circuit (IC) design teams. These design management platforms are a valuable help in analog IC design but they are still far behind the development stage of design automation tools already available for digital design. Therefore, the development of new CAD tools and design methodologies for analog and mixed-signal ICs is ess- tial to increase the designer's productivity and reduce design productivitygap. The work presented in this book describes a new design automation approach to the problem of sizing analog ICs.

This book presents a novel logarithmic conversion architecture based on cross-coupled inverter. An overview of the current state of the art of logarithmic converters is given where most conventional logarithmic analog-to-digital converter architectures are derived or adapted from linear analog-to-digital converter architectures, implying the use of analog building blocks such as amplifiers. The conversion architecture proposed in this book differs from the conventional logarithmic architectures. Future possible studies on integrating calibration in the voltage to time conversion element and work on an improved conversion architecture derived from the architecture are also presented in this book.

The microelectronics market, with special emphasis to the production of complex mixed-signal systems-on-chip (SoC), is driven by three main dynamics, time-- market, productivity and managing complexity. Pushed by the progress in na- meter technology, the design teams are facing a curve of complexity that grows exponentially, thereby slowing down the productivity design rate. Analog design automation tools are not developing at the same pace of technology, once custom design, characterized by decisions taken at each step of the analog design flow, - lies most of the time on designer knowledge and expertise. Actually, the use of - sign management platforms, like the Cadences Virtuoso platform, with a set of - tegrated CAD tools and database facilities to deal with the design transformations from the system level to the physical implementation, can significantly speed-up the design process and enhance the productivity of analog/mixed-signal integrated circuit (IC) design teams. These design management platforms are a valuable help in analog IC design but they are still far behind the development stage of design automation tools already available for digital design. Therefore, the development of new CAD tools and design methodologies for analog and mixed-signal ICs is ess- tial to increase the designer's productivity and reduce design productivitygap. The work presented in this book describes a new design automation approach to the problem of sizing analog ICs.

This book consists of the research, design and implementation, from sizing to layout with parasitic extraction and yield estimation, of a low-power, low-noise amplifier for biomedical and healthcare applications of bio-potential signals, particularly focusing on the electromyography and electrooculography. These signals usually operate in different broadbands, yet follow an impulse-shape transmission, hence being suitable to be applied and detected by the same receiver.

In this book, innovative research using artificial neural networks (ANNs) is conducted to automate the placement task in analog integrated circuit layout design, by creating a generalized model that can generate valid layouts at push-button speed. Further, it exploits ANNs' generalization and push-button speed prediction (once fully trained) capabilities, and details the optimal description of the input/output data relation. The description developed here is chiefly reflected in two of the system's characteristics: the shape of the input data and the minimized loss function. In order to address the latter, abstract and segmented descriptions of both the input data and the objective behavior are developed, which allow the model to identify, in newer scenarios, sub-blocks which can be found in the input data. This approach yields device-level descriptions of the input topology that, for each device, focus on describing its relation to every other device in the topology. By means of these descriptions, an unfamiliar overall topology can be broken down into devices that are subject to the same constraints as a device in one of the training topologies. In the experimental results chapter, the trained ANNs are used to produce a variety of valid placement solutions even beyond the scope of the training/validation sets, demonstrating the model's effectiveness in terms of identifying common components between newer topologies and reutilizing the acquired knowledge. Lastly, the methodology used can readily adapt to the given problem's context (high label production cost), resulting in an efficient, inexpensive and fast model.

This book investigates the application of promising machine learning techniques to address two problems: (i) how to find profitable pairs while constraining the search space and (ii) how to avoid long decline periods due to prolonged divergent pairs. It also proposes the integration of an unsupervised learning algorithm, OPTICS, to handle problem (i), and demonstrates that the suggested technique can outperform the common pairs search methods, achieving an average portfolio Sharpe ratio of 3.79, in comparison to 3.58 and 2.59 obtained using standard approaches. For problem (ii), the authors introduce a forecasting-based trading model capable of reducing the periods of portfolio decline by 75%. However, this comes at the expense of decreasing overall profitability. The authors also test the proposed strategy using an ARMA model, an LSTM and an LSTM encoder-decoder.

This book introduces readers to a variety of tools for automatic analog integrated circuit (IC) sizing and optimization. The authors provide a historical perspective on the early methods proposed to tackle automatic analog circuit sizing, with emphasis on the methodologies to size and optimize the circuit, and on the methodologies to estimate the circuit's performance. The discussion also includes robust circuit design and optimization and the most recent advances in layout-aware analog sizing approaches. The authors describe a methodology for an automatic flow for analog IC design, including details of the inputs and interfaces, multi-objective optimization techniques, and the enhancements made in the base implementation by using machine leaning techniques. The Gradient model is discussed in detail, along with the methods to include layout effects in the circuit sizing. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. An extensive set of application examples is included to demonstrate the capabilities and features of the methodologies described.

This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.

This work presents a new approach to portfolio composition in the stock market. It incorporates a fundamental approach using financial ratios and technical indicators with a Multi-Objective Evolutionary Algorithms to choose the portfolio composition with two objectives the return and the risk. Two different chromosomes are used for representing different investment models with real constraints equivalents to the ones faced by managers of mutual funds, hedge funds, and pension funds. To validate the present solution two case studies are presented for the SP&500 for the period June 2010 until end of 2012. The simulations demonstrates that stock selection based on financial ratios is a combination that can be used to choose the best companies in operational terms, obtaining returns above the market average with low variances in their returns. In this case the optimizer found stocks with high return on investment in a conjunction with high rate of growth of the net income and a high profit margin. To obtain stocks with high valuation potential it is necessary to choose companies with a lower or average market capitalization, low PER, high rates of revenue growth and high operating leverage

This work addresses the research and development of an innovative optimization kernel applied to analog integrated circuit (IC) design. Particularly, this works describes the modifications inside the AIDA Framework, an electronic design automation framework fully developed by at the Integrated Circuits Group-LX of the Instituto de Telecomunicacoes, Lisbon. It focusses on AIDA-CMK, by enhancing AIDA-C, which is the circuit optimizer component of AIDA, with a new multi-objective multi-constraint optimization module that constructs a base for multiple algorithm implementations. The proposed solution implements three approaches to multi-objective multi-constraint optimization, namely, an evolutionary approach with NSGAII, a swarm intelligence approach with MOPSO and stochastic hill climbing approach with MOSA. Moreover, the implemented structure allows the easy hybridization between kernels transforming the previous simple NSGAII optimization module into a more evolved and versatile module supporting multiple single and multi-kernel algorithms. The three multi-objective optimization approaches were validated with CEC2009 benchmarks to constrained multi-objective optimization and tested with real analog IC design problems. The achieved results were compared in terms of performance, using statistical results obtained from multiple independent runs. Finally, some hybrid approaches were also experimented, giving a foretaste to a wide range of opportunities to explore in future work.