The advances in microsystems offer new opportunities and capabilities to develop systems for biomedical applications, such as diagnostics and therapy. There is a need for a comprehensive treatment of microsystems and in particular for an understanding of performance limits associated with the shrinking scale of microsystems. The new edition of Microsystems for Bioelectronics addresses those needs and represents a major revision, expansion and advancement of the previous edition. This book considers physical principles and trends in extremely scaled autonomous microsystems such as integrated intelligent sensor systems, with a focus on energy minimization. It explores the implications of energy minimization on device and system architecture. It further details behavior of electronic components and its implications on system-level scaling and performance limits. In particular, fundamental scaling limits for energy sourcing, sensing, memory, computation and communication subsystems are developed and new applications such as optical, magnetic and mechanical sensors are presented. The new edition of this well-proven book with its unique focus and interdisciplinary approach shows the complexities of the next generation of nanoelectronic microsystems in a simple and illuminating view, and is aimed for a broad audience within the engineering and biomedical community.

Wave Pipelining: Theory and CMOS Implementation provides a coherent presentation of the theory of wave pipelined operation of digital circuits and discusses practical design techniques for the realization of wave pipelined circuits in CMOS technology. Wave pipeling is a timing methodology used in digital systems to enhance performance while conserving the number of data registers used. This is achieved by applying new data to the inputs of a combinatorial logic block before the previous outputs are available. In contrast to conventional pipelining, system performance is limited by differences in maximum and minimum circuit delay rather than maximum circuit delays. Realization of practical systems using this technique requires accurate system level and circuit level timing analysis. At the system level, timing constraints identifying valid regions of operation for correct clocking of wave pipelined circuits are presented. Both single stage and multiple stage systems including feedback are considered. At the circuit level, since performance is determined by the maximum circuit delay difference, highly accurate estimates of both maximum and minimum delays are needed. Thus, timing analysis based on traditional gate delay models is not sufficient. For CMOS circuits, data dependent delay models considering the effect of simultaneous multiple input switchings must be used. An algorithm using these delay models for accurate analysis of small to medium sized circuits is implemented in a prototype timing analyzer, XTV. Results are given for a set of benchmark circuits.

Wave Pipelining: Theory and CMOS Implementation provides a coherent presentation of the theory of wave pipelined operation of digital circuits and discusses practical design techniques for the realization of wave pipelined circuits in CMOS technology. Wave pipeling is a timing methodology used in digital systems to enhance performance while conserving the number of data registers used. This is achieved by applying new data to the inputs of a combinatorial logic block before the previous outputs are available. In contrast to conventional pipelining, system performance is limited by differences in maximum and minimum circuit delay rather than maximum circuit delays. Realization of practical systems using this technique requires accurate system level and circuit level timing analysis. At the system level, timing constraints identifying valid regions of operation for correct clocking of wave pipelined circuits are presented. Both single stage and multiple stage systems including feedback are considered. At the circuit level, since performance is determined by the maximum circuit delay difference, highly accurate estimates of both maximum and minimum delays are needed.Thus, timing analysis based on traditional gate delay models is not sufficient. For CMOS circuits, data dependent delay models considering the effect of simultaneous multiple input switchings must be used. An algorithm using these delay models for accurate analysis of small to medium sized circuits is implemented in a prototype timing analyzer, XTV. Results are given for a set of benchmark circuits.