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This book provides readers with a detailed reference regarding two
of the most important long-term reliability and aging effects on
nanometer integrated systems, electromigrations (EM) for
interconnect and biased temperature instability (BTI) for CMOS
devices. The authors discuss in detail recent developments in the
modeling, analysis and optimization of the reliability effects from
EM and BTI induced failures at the circuit, architecture and system
levels of abstraction. Readers will benefit from a focus on topics
such as recently developed, physics-based EM modeling, EM modeling
for multi-segment wires, new EM-aware power grid analysis, and
system level EM-induced reliability optimization and management
techniques. Reviews classic Electromigration (EM) models, as well
as existing EM failure models and discusses the limitations of
those models; Introduces a dynamic EM model to address transient
stress evolution, in which wires are stressed under time-varying
current flows, and the EM recovery effects. Also includes new,
parameterized equivalent DC current based EM models to address the
recovery and transient effects; Presents a cross-layer approach to
transistor aging modeling, analysis and mitigation, spanning
multiple abstraction levels; Equips readers for EM-induced dynamic
reliability management and energy or lifetime optimization
techniques, for many-core dark silicon microprocessors, embedded
systems, lower power many-core processors and datacenters.
This book provides readers with a detailed reference regarding two
of the most important long-term reliability and aging effects on
nanometer integrated systems, electromigrations (EM) for
interconnect and biased temperature instability (BTI) for CMOS
devices. The authors discuss in detail recent developments in the
modeling, analysis and optimization of the reliability effects from
EM and BTI induced failures at the circuit, architecture and system
levels of abstraction. Readers will benefit from a focus on topics
such as recently developed, physics-based EM modeling, EM modeling
for multi-segment wires, new EM-aware power grid analysis, and
system level EM-induced reliability optimization and management
techniques. Reviews classic Electromigration (EM) models, as well
as existing EM failure models and discusses the limitations of
those models; Introduces a dynamic EM model to address transient
stress evolution, in which wires are stressed under time-varying
current flows, and the EM recovery effects. Also includes new,
parameterized equivalent DC current based EM models to address the
recovery and transient effects; Presents a cross-layer approach to
transistor aging modeling, analysis and mitigation, spanning
multiple abstraction levels; Equips readers for EM-induced dynamic
reliability management and energy or lifetime optimization
techniques, for many-core dark silicon microprocessors, embedded
systems, lower power many-core processors and datacenters.
Model order reduction (MOR) techniques reduce the complexity of
VLSI designs, paving the way to higher operating speeds and smaller
feature sizes. This book presents a systematic introduction to, and
treatment of, the key MOR methods employed in general linear
circuits, using real-world examples to illustrate the advantages
and disadvantages of each algorithm. Following a review of
traditional projection-based techniques, coverage progresses to
more advanced MOR methods for VLSI design, including HMOR, passive
truncated balanced realization (TBR) methods, efficient inductance
modeling via the VPEC model, and structure-preserving MOR
techniques. Where possible, numerical methods are approached from
the CAD engineer's perspective, avoiding complex mathematics and
allowing the reader to take on real design problems and develop
more effective tools. With practical examples and over 100
illustrations, this book is suitable for researchers and graduate
students of electrical and computer engineering, as well as
practitioners working in the VLSI design industry.
Model order reduction (MOR) techniques reduce the complexity of
VLSI designs, paving the way to higher operating speeds and smaller
feature sizes. This book presents a systematic introduction to, and
treatment of, the key MOR methods employed in general linear
circuits, using real-world examples to illustrate the advantages
and disadvantages of each algorithm. Following a review of
traditional projection-based techniques, coverage progresses to
more advanced MOR methods for VLSI design, including HMOR, passive
truncated balanced realization (TBR) methods, efficient inductance
modeling via the VPEC model, and structure-preserving MOR
techniques. Where possible, numerical methods are approached from
the CAD engineer's perspective, avoiding complex mathematics and
allowing the reader to take on real design problems and develop
more effective tools. With practical examples and over 100
illustrations, this book is suitable for researchers and graduate
students of electrical and computer engineering, as well as
practitioners working in the VLSI design industry.
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