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The workshop on Scalable Shared Memory Multiprocessors took place
on May 26 and 27 1990 at the Stouffer Madison Hotel in Seattle,
Washington as a prelude to the 1990 International Symposium on
Computer Architecture. About 100 participants listened for two days
to the presentations of 22 invited The motivation for this workshop
was to speakers, from academia and industry. promote the free
exchange of ideas among researchers working on shared-memory
multiprocessor architectures. There was ample opportunity to argue
with speakers, and certainly participants did not refrain a bit
from doing so. Clearly, the problem of scalability in shared-memory
multiprocessors is still a wide-open question. We were even unable
to agree on a definition of "scalability." Authors had more than
six months to prepare their manuscript, and therefore the papers
included in this proceedings are refinements of the speakers'
presentations, based on the criticisms received at the workshop. As
a result, 17 authors contributed to these proceedings. We wish to
thank them for their diligence and care. The contributions in these
proceedings can be partitioned into four categories 1. Access Order
and Synchronization 2. Performance 3. Cache Protocols and
Architectures 4. Distributed Shared Memory Particular topics on
which new ideas and results are presented in these proceedings
include: efficient schemes for combining networks, formal
specification of shared memory models, correctness of trace-driven
simulations, synchronization, various coherence protocols, ."
Cache And Interconnect Architectures In Multiprocessors Eilat,
Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia
Shreekant S. Thakkar SequentComputerSystems The aim of the workshop
was to bring together researchers working on cache coherence
protocols for shared-memory multiprocessors with various
interconnect architectures. Shared-memory multiprocessors have
become viable systems for many applications. Bus based
shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax)
are currently limited to 32 processors. The fIrst goal of the
workshop was to learn about the performance ofapplications on
current cache-based systems. The second goal was to learn about new
network architectures and protocols for future scalable systems.
These protocols and interconnects would allow shared-memory
architectures to scale beyond current imitations. The workshop had
20 speakers who talked about their current research. The
discussions were lively and cordial enough to keep the participants
away from the wonderful sand and sun for two days. The participants
got to know each other well and were able to share their thoughts
in an informal manner. The workshop was organized into several
sessions. The summary of each session is described below. This book
presents revisions of some of the papers presented at the
workshop."
The workshop on Scalable Shared Memory Multiprocessors took place
on May 26 and 27 1990 at the Stouffer Madison Hotel in Seattle,
Washington as a prelude to the 1990 International Symposium on
Computer Architecture. About 100 participants listened for two days
to the presentations of 22 invited The motivation for this workshop
was to speakers, from academia and industry. promote the free
exchange of ideas among researchers working on shared-memory
multiprocessor architectures. There was ample opportunity to argue
with speakers, and certainly participants did not refrain a bit
from doing so. Clearly, the problem of scalability in shared-memory
multiprocessors is still a wide-open question. We were even unable
to agree on a definition of "scalability." Authors had more than
six months to prepare their manuscript, and therefore the papers
included in this proceedings are refinements of the speakers'
presentations, based on the criticisms received at the workshop. As
a result, 17 authors contributed to these proceedings. We wish to
thank them for their diligence and care. The contributions in these
proceedings can be partitioned into four categories 1. Access Order
and Synchronization 2. Performance 3. Cache Protocols and
Architectures 4. Distributed Shared Memory Particular topics on
which new ideas and results are presented in these proceedings
include: efficient schemes for combining networks, formal
specification of shared memory models, correctness of trace-driven
simulations, synchronization, various coherence protocols, ."
Cache And Interconnect Architectures In Multiprocessors Eilat,
Israel May 25-261989 Michel Dubois UniversityofSouthernCalifornia
Shreekant S. Thakkar SequentComputerSystems The aim of the workshop
was to bring together researchers working on cache coherence
protocols for shared-memory multiprocessors with various
interconnect architectures. Shared-memory multiprocessors have
become viable systems for many applications. Bus based
shared-memory systems (Eg. Sequent's Symmetry, Encore's Multimax)
are currently limited to 32 processors. The fIrst goal of the
workshop was to learn about the performance ofapplications on
current cache-based systems. The second goal was to learn about new
network architectures and protocols for future scalable systems.
These protocols and interconnects would allow shared-memory
architectures to scale beyond current imitations. The workshop had
20 speakers who talked about their current research. The
discussions were lively and cordial enough to keep the participants
away from the wonderful sand and sun for two days. The participants
got to know each other well and were able to share their thoughts
in an informal manner. The workshop was organized into several
sessions. The summary of each session is described below. This book
presents revisions of some of the papers presented at the
workshop."
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