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This monograph is based on the third author's lectures on computer
architecture, given in the summer semester 2013 at Saarland
University, Germany. It contains a gate level construction of a
multi-core machine with pipelined MIPS processor cores and a
sequentially consistent shared memory. The book contains the first
correctness proofs for both the gate level implementation of a
multi-core processor and also of a cache based sequentially
consistent shared memory. This opens the way to the formal
verification of synthesizable hardware for multi-core processors in
the future. Constructions are in a gate level hardware model and
thus deterministic. In contrast the reference models against which
correctness is shown are nondeterministic. The development of the
additional machinery for these proofs and the correctness proof of
the shared memory at the gate level are the main technical
contributions of this work.
This book presents a formal model for evaluating the cost
effectiveness of computer architectures. The model can cope with a
wide range of architectures, from CPU design to parallel
supercomputers. To illustrate the formal procedure of trade-off
analyses, several non-pipelined design alternatives for the
well-known RISC architecture called DLX are analyzed
quantitatively. It is formally proved that the interrupt mechanism
proposed for the DLX architecture handles nested interrupts
correctly.
In an appendix all programs to compute the cost and cycle time of
the designs described are listed in C code. Running these simple C
programs on a PC is sufficient to verify the results presented. The
book addresses design professionals and students in computer
architecture.
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