The FMICS 2007 workshopwas a?liated with the Computer-Aided Veri?cation (CAV) conference and held at the Park-Inn Hotel Alexanderplatz in Berlin, Germany, July 1-2, 2007. The aim of the FMICS workshop series is to provide a forum for researchers who are interested in the development and application of formal methods in industry. In particular, these workshops are intended to bring together scientists and practitioners who are active in the area of formal methods and interested in exchanging their experience in the industrial usage of these methods. These workshopsalso striveto promoteresearchand developmentfor the improvement of formal methods and tools for industrial applications. The topics for which contributions to FMICS 2007 were solicited included, but were not restricted to, the following: - Design, speci?cation, code generation and testing with formal methods - Veri?cation and validation of complex, distributed, real-time systems and embedded systems - Veri?cationand validationmethods that aimat circumventing shortcomings of existing methods with respect to their industrial applicability - Tools for the design and development of formal descriptions - Case studies and project reports on formal methods-related projects with industrial participation (e.g., safety critical systems, mobile systems, obje- based distributed systems) - Application of formal methods in standardization and industrial forums Theworkshopincluded?vesessionsofregularcontributionsandthreeinvited presentations, given by Charles Pecheur, Thomas Henzinger and G erard Berry."

Visual notations and languages continue to play a pivotal role in the design of complex software systems. In many cases visual notations are used to - scribe usage or interaction scenarios of software systems or their components. While representing scenarios using a visual notation is not the only possibility, a vast majority of scenario description languages is visual. Scenarios are used in telecommunications as Message Sequence Charts, in object-oriented system design as Sequence Diagrams, in reverse engineering as execution traces, and in requirements engineering as, for example, Use Case Maps or Life Sequence Charts. These techniques are used to capture requirements, to capture use cases in system documentation, to specify test cases, or to visualize runs of existing systems. They are often employed to represent concurrent systems that int- act via message passing or method invocation. In telecommunications, for more than 15 years the International Telecommunication Union has standardized the Message Sequence Charts (MSCs) notation in its recommendation Z. 120. More recently, with the emergence of UML as a predominant software design meth- ology, there has been special interest in the development of the sequence d- gram notation. As a result, the most recent version, 2. 0, of UML encompasses the Message Sequence Chart notation, including its hierarchical modeling f- tures. Other scenario-?avored diagrams in UML 2. 0 include activity diagrams and timing diagrams."

This book constitutes the refereed proceedings of the 9th International SPIN Workshop on Model Checking Software, held in Grenoble, France in April 2002 as a satellite event of ETAPS 2002.The 10 revised full research papers presented together with the abstracts of four invited papers or tutorials, three reports on work in progress, three invited industrial presentations, and four SPIN model checking tool descriptions were carefully reviewed and selected from 20 submissions. The book presents state-of-the-art results on the analysis and verifications of distributed and concurrent systems using the SPIN model checker as one of the most powerful and popular such system.

Increasing the designer's con dence that a piece of software or hardwareis c- pliant with its speci cation has become a key objective in the design process for software and hardware systems. Many approaches to reaching this goal have been developed, including rigorous speci cation, formal veri cation, automated validation, and testing. Finite-state model checking, as it is supported by the explicit-state model checkerSPIN, is enjoying a constantly increasingpopularity in automated property validation of concurrent, message based systems. SPIN has been in large parts implemented and is being maintained by Gerard Ho- mann, and is freely available via ftp fromnetlib.bell-labs.comor from URL http: //cm.bell-labs.com/cm/cs/what/spin/Man/README.html. The beauty of nite-state model checking lies in the possibility of building \push-button" validation tools. When the state space is nite, the state-space traversal will eventually terminate with a de nite verdict on the property that is being validated. Equally helpful is the fact that in case the property is inv- idated the model checker will return a counterexample, a feature that greatly facilitates fault identi cation. On the downside, the time it takes to obtain a verdict may be very long if the state space is large and the type of properties that can be validated is restricted to a logic of rather limited expressiveness.