Innovation in areas such as power supplies, size reduction, biocompatibility, durability and lifespan is leading to a rapid increase in the range of devices and applications in the field of implantable biomedical microsystems, which are used for monitoring, diagnosing, and controlling the activities of the human body.

This book provides comprehensive coverage of the fundamental design principles for implantable systems, as well as several major application areas. Each component in an implantable system is described, and major case studies demonstrate how these systems can be designed and optimized for specific design objectives.

Beside low-power signal processing electronics for implantable systems, further topics covered include signal processing hardware, sensor selection, wireless telemetry devices, new types of bio-transducers, power management solutions, system integration techniques, computational algorithms, device packaging, and security measures.

Case studies include studies on implantable neural signal processors, brain-machine interface (BMI) systems, implantable pressure sensors, pacemakers, neural prosthesis, cochlear implant systems, bladder pressure monitoring for treating urinary incontinence, and drug delivery for cancer patients.

Implantable Biomedical Microsystems is the first comprehensive coverage of bioimplantable system design providing an invaluable information source for researchers in Biomedical, Electrical, Computer, Systems, and Mechanical Engineering as well as Engineers involved in design and development of implantable electronic systems and, more generally, Engineers working on low-power wireless applications.
First time comprehensive coverage of system-level and component-level design and engineering aspects for implantable microsystems.
Provides insight into a wide range of proven applications and application specific design trade-offs of bioimplantable systems, including several major case studies.
Enables Engineers involved in development of implantable electronic systems to optimize applications for specific design objectives."

This book offers readers comprehensive coverage of security policy specification using new policy languages, implementation of security policies in Systems-on-Chip (SoC) designs - current industrial practice, as well as emerging approaches to architecting SoC security policies and security policy verification. The authors focus on a promising security architecture for implementing security policies, which satisfies the goals of flexibility, verification, and upgradability from the ground up, including a plug-and-play hardware block in which all policy implementations are enclosed. Using this architecture, they discuss the ramifications of designing SoC security policies, including effects on non-functional properties (power/performance), debug, validation, and upgrade. The authors also describe a systematic approach for "hardware patching", i.e., upgrading hardware implementations of security requirements safely, reliably, and securely in the field, meeting a critical need for diverse Internet of Things (IoT) devices. Provides comprehensive coverage of SoC security requirements, security policies, languages, and security architecture for current and emerging computing devices; Explodes myths and ambiguities in SoC security policy implementations, and provide a rigorous treatment of the subject; Demonstrates a rigorous, step-by-step approach to developing a diversity of SoC security policies; Introduces a rigorous, disciplined approach to "hardware patching", i.e., secure technique for updating hardware functionality of computing devices in-field; Includes discussion of current and emerging approaches for security policy verification.

This book analyzes energy and reliability as major challenges faced by designers of computing frameworks in the nanometer technology regime. The authors describe the existing solutions to address these challenges and then reveal a new reconfigurable computing platform, which leverages high-density nanoscale memory for both data storage and computation to maximize the energy-efficiency and reliability. The energy and reliability benefits of this new paradigm are illustrated and the design challenges are discussed. Various hardware and software aspects of this exciting computing paradigm are described, particularly with respect to hardware-software co-designed frameworks, where the hardware unit can be reconfigured to mimic diverse application behavior. Finally, the energy-efficiency of the paradigm described is compared with other, well-known reconfigurable computing platforms.

This book is about security in embedded systems and it provides an authoritative reference to all aspects of security in system-on-chip (SoC) designs. The authors discuss issues ranging from security requirements in SoC designs, definition of architectures and design choices to enforce and validate security policies, and trade-offs and conflicts involving security, functionality, and debug requirements. Coverage also includes case studies from the "trenches" of current industrial practice in design, implementation, and validation of security-critical embedded systems. Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs; Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs; Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security.

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.

This book introduces readers to various threats faced during design and fabrication by today's integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or "IC Overproduction," insertion of malicious circuits, referred as "Hardware Trojans", which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange of obfuscation keys- arguably the most critical element of hardware obfuscation.

This book, for the first time, provides comprehensive coverage on malicious modification of electronic hardware, also known as, hardware Trojan attacks, highlighting the evolution of the threat, different attack modalities, the challenges, and diverse array of defense approaches. It debunks the myths associated with hardware Trojan attacks and presents practical attack space in the scope of current business models and practices. It covers the threat of hardware Trojan attacks for all attack surfaces; presents attack models, types and scenarios; discusses trust metrics; presents different forms of protection approaches - both proactive and reactive; provides insight on current industrial practices; and finally, describes emerging attack modes, defenses and future research pathways.

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

The research community lacks both the capability to explain the effectiveness of existing techniques and the metrics to predict the security properties and vulnerabilities of the next generation of nano-devices and systems. This book provides in-depth viewpoints on security issues and explains how nano devices and their unique properties can address the opportunities and challenges of the security community, manufacturers, system integrators, and end users. This book elevates security as a fundamental design parameter, transforming the way new nano-devices are developed. Part 1 focuses on nano devices and building security primitives. Part 2 focuses on emerging technologies and integrations.

The research community lacks both the capability to explain the effectiveness of existing techniques and the metrics to predict the security properties and vulnerabilities of the next generation of nano-devices and systems. This book provides in-depth viewpoints on security issues and explains how nano devices and their unique properties can address the opportunities and challenges of the security community, manufacturers, system integrators, and end users. This book elevates security as a fundamental design parameter, transforming the way new nano-devices are developed. Part 1 focuses on nano devices and building security primitives. Part 2 focuses on emerging technologies and integrations.

Hardware Security: A Hands-On Learning Approach provides a broad, comprehensive and practical overview of hardware security that encompasses all levels of the electronic hardware infrastructure. It covers basic concepts like advanced attack techniques and countermeasures that are illustrated through theory, case studies and well-designed, hands-on laboratory exercises for each key concept. The book is ideal as a textbook for upper-level undergraduate students studying computer engineering, computer science, electrical engineering, and biomedical engineering, but is also a handy reference for graduate students, researchers and industry professionals. For academic courses, the book contains a robust suite of teaching ancillaries. Users will be able to access schematic, layout and design files for a printed circuit board for hardware hacking (i.e. the HaHa board) that can be used by instructors to fabricate boards, a suite of videos that demonstrate different hardware vulnerabilities, hardware attacks and countermeasures, and a detailed description and user manual for companion materials.

This book provides an overview of current Intellectual Property (IP) based System-on-Chip (SoC) design methodology and highlights how security of IP can be compromised at various stages in the overall SoC design-fabrication-deployment cycle. Readers will gain a comprehensive understanding of the security vulnerabilities of different types of IPs. This book would enable readers to overcome these vulnerabilities through an efficient combination of proactive countermeasures and design-for-security solutions, as well as a wide variety of IP security and trust assessment and validation techniques. This book serves as a single-source of reference for system designers and practitioners for designing secure, reliable and trustworthy SoCs.

This book is about security in embedded systems and it provides an authoritative reference to all aspects of security in system-on-chip (SoC) designs. The authors discuss issues ranging from security requirements in SoC designs, definition of architectures and design choices to enforce and validate security policies, and trade-offs and conflicts involving security, functionality, and debug requirements. Coverage also includes case studies from the "trenches" of current industrial practice in design, implementation, and validation of security-critical embedded systems. Provides an authoritative reference and summary of the current state-of-the-art in security for embedded systems, hardware IPs and SoC designs; Takes a "cross-cutting" view of security that interacts with different design and validation components such as architecture, implementation, verification, and debug, each enforcing unique trade-offs; Includes high-level overview, detailed analysis on implementation, and relevant case studies on design/verification/debug issues related to IP/SoC security.

This book introduces readers to various threats faced during design and fabrication by today's integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or "IC Overproduction," insertion of malicious circuits, referred as "Hardware Trojans", which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange of obfuscation keys- arguably the most critical element of hardware obfuscation.

This book analyzes energy and reliability as major challenges faced by designers of computing frameworks in the nanometer technology regime. The authors describe the existing solutions to address these challenges and then reveal a new reconfigurable computing platform, which leverages high-density nanoscale memory for both data storage and computation to maximize the energy-efficiency and reliability. The energy and reliability benefits of this new paradigm are illustrated and the design challenges are discussed. Various hardware and software aspects of this exciting computing paradigm are described, particularly with respect to hardware-software co-designed frameworks, where the hardware unit can be reconfigured to mimic diverse application behavior. Finally, the energy-efficiency of the paradigm described is compared with other, well-known reconfigurable computing platforms.

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.