Low-Power Variation-Tolerant Design in Nanometer Silicon (Hardcover, 2011 Ed.)

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	November 2010
First published:	2011
Editors:	Swarup Bhunia • Saibal Mukhopadhyay
Dimensions:	235 x 155 x 25mm (L x W x T)
Format:	Hardcover
Pages:	440
Edition:	2011 Ed.
ISBN-13:	978-1-4419-7417-4
Categories:	Books > Professional & Technical > Technology: general issues > Technical design > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN:	1-4419-7417-2
Barcode:	9781441974174

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