Low Power Design in Deep Submicron Electronics deals with the different aspects of low power design for deep submicron electronics at all levels of abstraction from system level to circuit level and technology. Its objective is to guide industrial and academic engineers and researchers in the selection of methods, technologies and tools and to provide a baseline for further developments. Furthermore the book has been written to serve as a textbook for postgraduate student courses. In order to achieve both goals, it is structured into different chapters each of which addresses a different phase of the design, a particular level of abstraction, a unique design style or technology. These design-related chapters are amended by motivations in Chapter 2, which presents visions both of future low power applications and technology advancements, and by some advanced case studies in Chapter 9. From the Foreword: ... This global nature of design for low power was well understood by Wolfgang Nebel and Jean Mermet when organizing the NATO workshop which is the origin of the book. They invited the best experts in the field to cover all aspects of low power design. As a result the chapters in this book are covering deep-submicron CMOS digital system design for low power in a systematic way from process technology all the way up to software design and embedded software systems. Low Power Design in Deep Submicron Electronics is an excellent guide for the practicing engineer, the researcher and the student interested in this crucial aspect of actual CMOS design. It contains about a thousand references to all aspects of the recent five years of feverish activity in this exciting aspect of design.' Hugo de Man Professor, K.U. Leuven, Belgium Senior Research Fellow, IMEC, Belgium

Decreasing power dissipation per logic function has become a primary concern in virtually all CMOS system chips designed today as a result of the relentless progress in processing technology that has led us into the deep-submicron age. Evolution from 1 micron to 0.1 micron lithography in the next decade will not be possible without a change in the way we design CMOS systems. But power reduction requires an overall optimisation, ranging from software compilation over instruction set design down to the introduction of much more parallelism in the architecture, the optimal use of memory hierarchy, new clocking strategies, use of asynchronous techniques, new CMOS circuit techniques and management of leakage currents in new low power technologies. Moreover, performance and power dissipation will come to be dominated by interconnect and thus completely new floor planning and place and route strategies are emerging. The chapters in this book present a systematic coverage of deep submicron CMOS digital system design for low power, from process technology all the way up to software design and embedded software systems. Audience: An excellent guide for the practising engineer, researcher and student interested in this crucial aspect of actual CMOS design.