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Books > Computing & IT > General theory of computing
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Delay Fault Testing for VLSI Circuits (Hardcover, 1998 ed.)
Loot Price: R4,302
Discovery Miles 43 020
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Delay Fault Testing for VLSI Circuits (Hardcover, 1998 ed.)
Series: Frontiers in Electronic Testing, 14
Expected to ship within 12 - 17 working days
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With the ever-increasing speed of integrated circuits, violations
of the performance specifications are becoming a major factor
affecting the product quality level. The need for testing timing
defects is further expected to grow with the current design trend
of moving towards deep submicron devices. After a long period of
prevailing belief that high stuck-at fault coverage is sufficient
to guarantee high quality of shipped products, the industry is now
forced to rethink other types of testing. Delay testing has been a
topic of extensive research both in industry and in academia for
more than a decade. As a result, several delay fault models and
numerous testing methodologies have been proposed. Delay Fault
Testing for VLSI Circuits presents a selection of existing delay
testing research results. It combines introductory material with
state-of-the-art techniques that address some of the current
problems in delay testing. Delay Fault Testing for VLSI Circuits
covers some basic topics such as fault modeling and test
application schemes for detecting delay defects. It also presents
summaries and conclusions of several recent case studies and
experiments related to delay testing. A selection of delay testing
issues and test techniques such as delay fault simulation, test
generation, design for testability and synthesis for testability
are also covered. Delay Fault Testing for VLSI Circuits is intended
for use by CAD and test engineers, researchers, tool developers and
graduate students. It requires a basic background in digital
testing. The book can used as supplementary material for a
graduate-level course on VLSI testing.
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