Networks on Chip presents a variety of topics, problems and
approaches with the common theme to systematically organize the
on-chip communication in the form of a regular, shared
communication network on chip, an NoC for short.
As the number of processor cores and IP blocks integrated on a
single chip is steadily growing, a systematic approach to design
the communication infrastructure becomes necessary. Different
variants of packed switched on-chip networks have been proposed by
several groups during the past two years. This book summarizes the
state of the art of these efforts and discusses the major issues
from the physical integration to architecture to operating systems
and application interfaces. It also provides a guideline and vision
about the direction this field is moving to. Moreover, the book
outlines the consequences of adopting design platforms based on
packet switched network. The consequences may in fact be far
reaching because many of the topics of distributed systems,
distributed real-time systems, fault tolerant systems, parallel
computer architecture, parallel programming as well as traditional
system-on-chip issues will appear relevant but within the
constraints of a single chip VLSI implementation.
The book is organized in three parts. The first deals with
system design and methodology issues. The second presents problems
and solutions concerning the hardware and the basic communication
infrastructure. Finally, the third part covers operating system,
embedded software and application. However, communication from the
physical to the application level is a central theme throughout the
book.
The book serves as an excellent reference source and may be used
as a text for advanced courses on the subject.
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