VHDL Coding Styles and Methodologies, Second Edition is a follow-up
book to the first edition of the same book and to VHDL Answers to
Frequently Asked Questions, first and second editions. This new
edition provides practical information on reusable software
methodologies for the design of bus functional models for
testbenches. It provides guidelines in the use of VHDL for
synthesis. All VHDL code described in the book is on a companion
CD, which also includes the GNU toolsite with EMACS
language-sensitive editor (with VHDL, Verilog, and other language
templates), and TSHELL tools that emulate a Unix shell. Model
Technology graciously included an evaluation version of ModelSim, a
recognized industry standard VHDL/Verilog compiler and simulator
that supports easy viewing of the models under analysis, along with
many debug features. In addition, Synplicity is kindly making
available an evaluation version of Synplicity, a very efficient,
user-friendly and easy-to-use FPGA synthesis tool. Synplify
provides a user with both the RTL and gate-level views of the
synthesized model, and a performance report of the design.
Optimization mechanisms are provided in the tool.
Intended for professional engineers as well as students, it is
organized in thirteen chapters, each covering a separate aspect of
the language, with complete examples. It provides a practical
approach to learning VHDL. Combining methodologies and coding
styles, along with VHDL rules, leads the reader in the right
direction from the beginning.
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