Guide to Computer Processor Architecture - A RISC-V Approach, with High-Level Synthesis (Paperback, 1st ed. 2023)

The book presents a succession of RISC-V processor implementations in increasing difficulty (non pipelined, pipelined, deeply pipelined, multithreaded, multicore). Each implementation is shown as an HLS (High Level Synthesis) code in C++ which can really be synthesized and tested on an FPGA based development board (such a board can be freely obtained from the Xilinx University Program targeting the university professors). The book can be useful for three reasons. First, it is a novel way to introduce computer architecture. The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promised to become the machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the High Level Synthesis, a tool which is able to translate a C program into an IP (Intellectual Property). Hence, the book can serve to engineers willing to implement processors on FPGA and to researchers willing to develop RISC-V based hardware simulators.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Series:	Undergraduate Topics in Computer Science
Release date:	February 2023
First published:	2023
Authors:	Bernard Goossens
Dimensions:	235 x 155mm (L x W)
Format:	Paperback
Pages:	468
Edition:	1st ed. 2023
ISBN-13:	978-3-03-118022-4
Categories:	Books > Computing & IT > General theory of computing > Data structures Books > Computing & IT > Computer programming > Algorithms & procedures Books > Computing & IT > Computer programming > Software engineering Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Books > Computing & IT > Computer hardware & operating systems > Operating systems & graphical user interfaces (GUIs) > General
LSN:	3-03-118022-4
Barcode:	9783031180224

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