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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (Hardcover, 2014 ed.) Loot Price: R3,468

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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (Hardcover, 2014 ed.): Brandon Noia, Krishnendu...

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (Hardcover, 2014 ed.)

Brandon Noia, Krishnendu Chakrabarty

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List price ~~R3,777~~ Loot Price R3,468 Discovery Miles 34 680 | Repayment Terms: R325 pm x 12* You Save R309 (8%)

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This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.

General

Imprint:	Springer International Publishing AG
Country of origin:	Switzerland
Release date:	December 2013
First published:	2014
Authors:	Brandon Noia • Krishnendu Chakrabarty
Dimensions:	235 x 155 x 16mm (L x W x T)
Format:	Hardcover
Pages:	245
Edition:	2014 ed.
ISBN-13:	978-3-319-02377-9
Categories:	Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Electronic devices & materials > General Promotions
LSN:	3-319-02377-2
Barcode:	9783319023779