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Wafer Level 3-D ICs Process Technology (Paperback, 1st ed. Softcover of orig. ed. 2009) Loot Price: R4,044
Discovery Miles 40 440
Repayment Terms: R379 pm x 12*
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Wafer Level 3-D ICs Process Technology (Paperback, 1st ed. Softcover of orig. ed. 2009): Chuan Seng Tan, Ronald J. Gutmann, L....

Wafer Level 3-D ICs Process Technology (Paperback, 1st ed. Softcover of orig. ed. 2009)

Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif

Series: Integrated Circuits and Systems

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Loot Price R4,044 Discovery Miles 40 440 | Repayment Terms: R379 pm x 12*

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This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

General

Imprint: Springer-Verlag New York
Country of origin: United States
Series: Integrated Circuits and Systems
Release date: December 2010
First published: 2009
Editors: Chuan Seng Tan • Ronald J. Gutmann • L. Rafael Reif
Dimensions: 235 x 155 x 19mm (L x W x T)
Format: Paperback
Pages: 410
Edition: 1st ed. Softcover of orig. ed. 2009
ISBN-13: 978-1-4419-4562-4
Categories: Books > Professional & Technical > Technology: general issues > Engineering: general
Books > Professional & Technical > Mechanical engineering & materials > Materials science > General
Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Electronic devices & materials > General
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LSN: 1-4419-4562-8
Barcode: 9781441945624

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