Hierarchical Modeling for VLSI Circuit Testing (Hardcover, 1990 ed.)

Test generation is one of the most difficult tasks facing the designer of complex VLSI-based digital systems. Much of this difficulty is attributable to the almost universal use in testing of low, gate-level circuit and fault models that predate integrated circuit technology. It is long been recognized that the testing prob lem can be alleviated by the use of higher-level methods in which multigate modules or cells are the primitive components in test generation; however, the development of such methods has proceeded very slowly. To be acceptable, high-level approaches should be applicable to most types of digital circuits, and should provide fault coverage comparable to that of traditional, low-level methods. The fault coverage problem has, perhaps, been the most intractable, due to continued reliance in the testing industry on the single stuck-line (SSL) fault model, which is tightly bound to the gate level of abstraction. This monograph presents a novel approach to solving the foregoing problem. It is based on the systematic use of multibit vectors rather than single bits to represent logic signals, including fault signals. A circuit is viewed as a collection of high-level components such as adders, multiplexers, and registers, interconnected by n-bit buses. To match this high-level circuit model, we introduce a high-level bus fault that, in effect, replaces a large number of SSL faults and allows them to be tested in parallel. However, by reducing the bus size from n to one, we can obtain the traditional gate-level circuit and models."

General

Imprint:	Springer
Country of origin:	Netherlands
Series:	The Springer International Series in Engineering and Computer Science, 89
Release date:	December 1989
First published:	1990
Authors:	Debashis Bhattacharya • John P. Hayes
Dimensions:	235 x 155 x 11mm (L x W x T)
Format:	Hardcover
Pages:	160
Edition:	1990 ed.
ISBN-13:	978-0-7923-9058-9
Categories:	Books > Professional & Technical > General Books > Computing & IT > General theory of computing > General Books > Computing & IT > Applications of computing > General Promotions
LSN:	0-7923-9058-X
Barcode:	9780792390589

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