Job Scheduling Strategies for Parallel Processing - IPDPS 2000 Workshop, JSSPP 2000, Cancun, Mexico, May 1, 2000 Proceedings (Paperback, 2000 ed.)

This volume contains the papers presented at the sixth workshop on Job Sched- ing Strategies for Parallel Processing, which was held in conjunction with the IPDPS 2000 Conference in Cancun, Mexico, on 1 May 2000. The papers have been through a complete refereeing process, with the full version being read and evaluated by ?ve to seven members of the program committee. We would like to take this opportunity to thank the program committee, Andrea Arpaci-Dusseau, Fran Berman, Steve Chapin, Allen Downey, Allan Gottlieb, Atsushi Hori, Phil Krueger, Richard Lagerstrom, Virginia Lo, Reagan Moore, Bill Nitzberg, Uwe Schwiegelshohn, and Mark Squillante, for an excellent job. Thanks are also due to the authors for their submissions, presentations, and ?nal revisions for this volume. Finally, we would like to thank the MIT Laboratory for Computer S- ence and the Computer Science Institute at the Hebrew University for the use of their facilities in the preparation of these proceedings. This was the sixth annual workshop in this series, which re?ects the continued interest in this ?eld. The previous ?ve were held in conjunction with IPPS'95 through IPPS/SPDP'99. Their proceedings are available from Springer-Verlag as volumes 949, 1162, 1291, 1459, and 1659 of the Lecture Notes in Computer Science series. The last two are also available on-line from Springer LINK.

General

Imprint:	Springer-Verlag
Country of origin:	Germany
Series:	Lecture Notes in Computer Science, 1911
Release date:	2001
First published:	2000
Editors:	Dror G. Feitelson • Larry Rudolph
Dimensions:	235 x 155 x 12mm (L x W x T)
Format:	Paperback
Pages:	209
Edition:	2000 ed.
ISBN-13:	978-3-540-41120-8
Categories:	Books > Computing & IT > General theory of computing > Data structures Books > Computing & IT > Computer programming > Algorithms & procedures Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design > Parallel processing Promotions
LSN:	3-540-41120-8
Barcode:	9783540411208

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