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Advanced ASIC Chip Synthesis - Using Synopsys (R) Design Compiler (TM) Physical Compiler (TM) and PrimeTime (R) (Paperback, 2nd ed. 2002. Softcover reprint of the original 2nd ed. 2002)
Loot Price: R6,542
Discovery Miles 65 420
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Advanced ASIC Chip Synthesis - Using Synopsys (R) Design Compiler (TM) Physical Compiler (TM) and PrimeTime (R) (Paperback, 2nd ed. 2002. Softcover reprint of the original 2nd ed. 2002)
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Advanced ASIC Chip Synthesis: Using Synopsys (R) Design Compiler
(R) Physical Compiler (R) and PrimeTime (R), Second Edition
describes the advanced concepts and techniques used towards ASIC
chip synthesis, physical synthesis, formal verification and static
timing analysis, using the Synopsys suite of tools. In addition,
the entire ASIC design flow methodology targeted for VDSM
(Very-Deep-Sub-Micron) technologies is covered in detail. The
emphasis of this book is on real-time application of Synopsys
tools, used to combat various problems seen at VDSM geometries.
Readers will be exposed to an effective design methodology for
handling complex, sub-micron ASIC designs. Significance is placed
on HDL coding styles, synthesis and optimization, dynamic
simulation, formal verification, DFT scan insertion, links to
layout, physical synthesis, and static timing analysis. At each
step, problems related to each phase of the design flow are
identified, with solutions and work-around described in detail. In
addition, crucial issues related to layout, which includes clock
tree synthesis and back-end integration (links to layout) are also
discussed at length. Furthermore, the book contains in-depth
discussions on the basis of Synopsys technology libraries and HDL
coding styles, targeted towards optimal synthesis solution. Target
audiences for this book are practicing ASIC design engineers and
masters level students undertaking advanced VLSI courses on ASIC
chip design and DFT techniques.
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