Hardware Component Modeling (Hardcover, 1996 ed.)

The VITAL specification addresses the issues of interoperability, backannotation and high performance simulation for sign-off quality ASIC libraries in VHDL. VITAL provides modeling guidelines and a set of pre-defined packages (containing pre-defined routines for modeling functionality and timing) to facilitate the acceleration of designs which use cells from a VITAL library. The VITAL Level-I guidelines constrain the modeling capabilities provided by VHDL in order to facilitate higher performance (Figure I). Accumulating "gains" Constrained "flexibility" Higher performance & Increased capacity Benefits Flexibility FujI VHDL 1076 Figure 1: VHDL and VITAL Even within the Level-I guidelines, there are several ways in which a model can be written. In this chapter, we highlight the various modeling trade-offs and provide guidelines which can be used for developing efficient models. We will also discuss the techniques that can be used by tool developers to accelerate the simulation of VIT AL based designs. 2.2. OVERVIEW OF A VITAL LEVEL-l ARCIDTECTURE The VITAL specification is versatile enough to support several modeling styles e.g., distributed delay style, pin-to-pin delay style etc. In general, a VITAL Level-I model can have the structure illustrated in Figure 2."

General

Imprint:	Springer
Country of origin:	Netherlands
Series:	Current Issues in Electronic Modeling, 5
Release date:	2001
First published:	1996
Editors:	Jean-Michel Berge • Oz Levia • Jacques Rouillard
Dimensions:	235 x 155 x 11mm (L x W x T)
Format:	Hardcover
Pages:	134
Edition:	1996 ed.
ISBN-13:	978-0-7923-9686-4
Categories:	Books > Professional & Technical > General Books > Computing & IT > General theory of computing > General Books > Computing & IT > Applications of computing > General
LSN:	0-7923-9686-3
Barcode:	9780792396864

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