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Verilog HDL Design Examples (Paperback)
Loot Price: R1,980
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Verilog HDL Design Examples (Paperback)
Expected to ship within 12 - 17 working days
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The Verilog language provides a means to model a digital system at
many levels of abstraction from a logic gate to a complex digital
system to a mainframe computer. The purpose of this book is to
present the Verilog language together with a wide variety of
examples, so that the reader can gain a firm foundation in the
design of the digital system using Verilog HDL. The Verilog
projects include the design module, the test bench module, and the
outputs obtained from the simulator that illustrate the complete
functional operation of the design. Where applicable, a detailed
review of the theory of the topic is presented together with the
logic design principles-including: state diagrams, Karnaugh maps,
equations, and the logic diagram. Numerous examples and homework
problems are included throughout. The examples include logical
operations, counters of different moduli, half adders, full adders,
a carry lookahead adder, array multipliers, different types of
Moore and Mealy machines, and arithmetic logic units (ALUs).
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