Welcome to Loot.co.za! Sign in / Register |Wishlists & Gift Vouchers |Help | Advanced search

Checkout
- Your Cart Price

Your cart

Your cart is empty

Books > Computing & IT > Computer programming > Programming languages

Buy Now

Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.) Loot Price: R2,975

Discovery Miles 29 750

Repayment Terms: R279 pm x 12*

Add to cart

Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.): Kothanda Umamageswaran, Sheetanshu L....

Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.)

Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

(sign in to rate)

Loot Price R2,975 Discovery Miles 29 750 | Repayment Terms: R279 pm x 12*

Expected to ship within 10 - 15 working days

Description
Details
Customer Reviews

Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

General

Imprint:	Springer
Country of origin:	Netherlands
Release date:	2001
First published:	1999
Authors:	Kothanda Umamageswaran • Sheetanshu L. Pandey • Philip A. Wilsey
Dimensions:	235 x 155 x 12mm (L x W x T)
Format:	Hardcover
Pages:	158
Edition:	1999 ed.
ISBN-13:	978-0-7923-8375-8
Categories:	Books > Computing & IT > General theory of computing > Systems analysis & design Books > Computing & IT > Computer programming > Programming languages > General Promotions
LSN:	0-7923-8375-3
Barcode:	9780792383758