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Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.) Loot Price: R2,746
Discovery Miles 27 460
Repayment Terms: R257 pm x 12*
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Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.): Kothanda Umamageswaran, Sheetanshu L....

Formal Semantics and Proof Techniques for Optimizing VHDL Models (Hardcover, 1999 ed.)

Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

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Loot Price R2,746 Discovery Miles 27 460 | Repayment Terms: R257 pm x 12*

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Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

General

Imprint: Springer
Country of origin: Netherlands
Release date: 2001
First published: 1999
Authors: Kothanda Umamageswaran • Sheetanshu L. Pandey • Philip A. Wilsey
Dimensions: 235 x 155 x 12mm (L x W x T)
Format: Hardcover
Pages: 158
Edition: 1999 ed.
ISBN-13: 978-0-7923-8375-8
Categories: Books > Computing & IT > General theory of computing > Systems analysis & design
Books > Computing & IT > Computer programming > Programming languages > General
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LSN: 0-7923-8375-3
Barcode: 9780792383758

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