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VLSI Test Principles and Architectures - Design for Testability (Hardcover, New) Loot Price: R1,354
Discovery Miles 13 540
Repayment Terms: R127 pm x 12*
VLSI Test Principles and Architectures - Design for Testability (Hardcover, New): Laung-terng Wang, Cheng-Wen Wu, Xiaoqing Wen

VLSI Test Principles and Architectures - Design for Testability (Hardcover, New)

Laung-terng Wang, Cheng-Wen Wu, Xiaoqing Wen; Contributions by Khader S. Abdel-Hafez, Soumendu Bhattacharya, Abhijit Chatterjee, Xinghao Chen, Kwang-Ting (Tim) Cheng, William Eklow, Michael S. Hsiao

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Loot Price R1,354 Discovery Miles 13 540 | Repayment Terms: R127 pm x 12*

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This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
. Most up-to-date coverage of design for testability.
. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books.
. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
. Lecture slides and exercise solutions for all chapters are now available.
. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

General

Imprint: Morgan Kaufmann Publishers In
Country of origin: United States
Release date: August 2006
First published: June 2006
Authors: Laung-terng Wang • Cheng-Wen Wu • Xiaoqing Wen
Contributors: Khader S. Abdel-Hafez • Soumendu Bhattacharya • Abhijit Chatterjee • Xinghao Chen • Kwang-Ting (Tim) Cheng • William Eklow • Michael S. Hsiao
Dimensions: 235 x 191 x 51mm (L x W x T)
Format: Hardcover
Pages: 808
Edition: New
ISBN-13: 978-0-12-370597-6
Categories: Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
Books > Academic & Education > Professional & Technical > Computing
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LSN: 0-12-370597-5
Barcode: 9780123705976

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