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Books > Computing & IT > Computer hardware & operating systems > Computer architecture & logic design
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A Systolic Array Optimizing Compiler (Paperback, Softcover reprint of the original 1st ed. 1989)
Loot Price: R2,635
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A Systolic Array Optimizing Compiler (Paperback, Softcover reprint of the original 1st ed. 1989)
Series: The Springer International Series in Engineering and Computer Science, 64
Expected to ship within 18 - 22 working days
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This book is a revision of my Ph. D. thesis dissertation submitted
to Carnegie Mellon University in 1987. It documents the research
and results of the compiler technology developed for the Warp
machine. Warp is a systolic array built out of custom,
high-performance processors, each of which can execute up to 10
million floating-point operations per second (10 MFLOPS). Under the
direction of H. T. Kung, the Warp machine matured from an academic,
experimental prototype to a commercial product of General Electric.
The Warp machine demonstrated that the scalable architecture of
high-peiformance, programmable systolic arrays represents a
practical, cost-effective solu tion to the present and future
computation-intensive applications. The success of Warp led to the
follow-on iWarp project, a joint project with Intel, to develop a
single-chip 20 MFLOPS processor. The availability of the highly
integrated iWarp processor will have a significant impact on
parallel computing. One of the major challenges in the development
of Warp was to build an optimizing compiler for the machine. First,
the processors in the xx A Systolic Array Optimizing Compiler array
cooperate at a fine granularity of parallelism, interaction between
processors must be considered in the generation of code for
individual processors. Second, the individual processors themselves
derive their performance from a VLIW (Very Long Instruction Word)
instruction set and a high degree of internal pipelining and
parallelism. The compiler contains optimizations pertaining to the
array level of parallelism, as well as optimizations for the
individual VLIW processors."
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