Verification Plans - The Five-Day Verification Strategy for Modern Hardware Verification Languages (Paperback, 2004 ed.)

Verification isjob one in today's modem design process. Statistics tell us that the verification process takes up a majority of the overall work. Chips that come back dead on arrival scream that verification is at fault for not finding the mistakes. How do we ensure success? After an accomplishment, have you ever had someone ask you, "Are you good or are you just lucky?"? Many design projects depend on blind luck in hopes that the chip will work. Other's, just adamantly rely on their own abilities to bring the chip to success. ill either case, how can we tell the difference between being good or lucky? There must be a better way not to fail. Failure. No one likes to fail. ill his book, "The Logic of Failure", Dietrich Domer argues that failure does not just happen. A series of wayward steps leads to disaster. Often these wayward steps are not really logical, decisive steps, but more like default omissions. Anti-planning if you will, an ad-hoc approach to doing something. To not plan then, is to fail.

General

Imprint:	Springer-Verlag New York
Country of origin:	United States
Release date:	November 2012
First published:	2004
Authors:	Peet James
Dimensions:	235 x 155 x 13mm (L x W x T)
Format:	Paperback
Pages:	229
Edition:	2004 ed.
ISBN-13:	978-1-4613-5094-1
Categories:	Books > Computing & IT > Computer hardware & operating systems > General Books > Professional & Technical > Technology: general issues > Technical design > Computer aided design (CAD) Books > Professional & Technical > Energy technology & engineering > Electrical engineering > General Books > Professional & Technical > Electronics & communications engineering > Electronics engineering > Circuits & components
LSN:	1-4613-5094-8
Barcode:	9781461350941

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